Multi-bit digital signal isolator
AssigneeAnalog Devices, Inc.
InventorEric Gaalaas
Life of this patent
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Abstract
The invention is directed to a multi-bit digital signal isolation system including a plurality of micro-transformers, each having a primary winding and a secondary winding, a transmitter circuit receiving a multi-bit signal and transmitting an encoded logic signal across the plurality of micro-transformers corresponding to the multi-bit signal, the primary winding of each micro-transformer receiving a signal corresponding to one of at least three possible states, and a receiver circuit receiving the encoded logic signal from the secondary windings of the plurality of transformers, decoding the encoded logic signal and reconstructing the received multi-bit signal based upon the decoded signal.
Claims25
A multi-bit digital signal isolator, comprising:
- a plurality of micro-transformers, each having a primary winding and a secondary winding;
- a transmitter circuit receiving a multi-bit word and transmitting an encoded logic signal across the plurality of micro-transformers in parallel corresponding to the multi-bit word, the primary winding of each micro-transformer receiving a signal corresponding to one of at least three possible states;
- and
- a receiver circuit receiving the encoded logic signal from the secondary windings of the plurality of transformers, decoding the encoded logic signal and reconstructing the received multi-bit word based upon the decoded signal,
- wherein said transmitter circuit further comprises a pulse generator generating the encoded logic signals by generating a signal with zero pulses, a signal with one pulse and a signal with two pulses corresponding to at least one of the three possible states.
A method of transmitting multi-bit signal across a digital signal isolator system, comprising:
- receiving an input multi-bit word;
- developing an encoded logic signal corresponding to the input multi-bit word;
- transmitting the encoded logic signal in parallel across a plurality of micro-transformers, wherein there are fewer transformers than bits in the multi-bit word;
- and
- decoding the encoded logic signal and reconstructing the received multi-bit word based upon the decoded signal,
- wherein the encoded logic signals are generated by a pulse generator and the encoded logic signals are a signal with zero pulses, a signal with one pulse and a signal with two pulses.
A multi-bit isolation system, comprising:
- a plurality of isolation channels, each to transmit a respective signal across an isolation barrier;
- a transmit circuit, provided on a first side of the isolation barrier, that receives an input signal having a predetermined bit-width and having outputs coupled to the isolation channels;
- and
- a receive circuit provided on a second side of the isolation barrier, having inputs coupled to the isolation channels and having an output for a reconstructed input signal,
- wherein a number of isolation channels is fewer than a number of bits in the bit-width, the isolation channels receive signals generated by a pulse generator that include a signal with zero pulses, a signal with one pulse and a signal with two pulses.
A method of transmitting a multi-bit word across a digital signal isolator system, comprising:
- receiving an input multi-bit word;
- developing an encoded logic signal corresponding to the input multi-bit word;
- transmitting the encoded logic signal in parallel across a plurality of isolation channels, wherein each isolation channel receives a signal corresponding to one of at least three possible states;
- and
- decoding the encoded logic signal and reconstructing the received multi-bit word based upon the decoded signal,
- wherein the three possible states include a signal with zero pulses, a signal with one pulse and a signal with two pulses, and a number of the isolation channels is fewer than the number of bits in the multi-bit word.
An isolation system for transmission of a multi-bit binary word, comprising:
- a plurality of isolation channels;
- a transmit circuit, provided on a first side of an isolation barrier, that converts the binary word into a set of output values having a base greater than two and outputs, to each isolation channel in parallel, transmission signals corresponding to a respective output value of the set of output values;
- and
- a receive circuit provided on a second side of the isolation barrier, that receives a set of input values from the isolation channel generated by the transmission signals and outputs a reconstructed binary word therefrom,
- wherein the set of output values includes a signal with zero pulses, a signal with one pulse and a signal with two pulses, and wherein a number of the isolation channels is fewer than the number of bits in the binary word.
Dependencies are inferred from the claim text.