Circuits and methods for DFE with reduced area and power consumption
AssigneeInternational Business Machines Corporation
InventorsJohn F. Bulzacchelli, Byungsub Kim
Life of this patent
Estimating the term…
Abstract
A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.
Claims11
A 1/n-rate decision feedback equalizer (DFE), wherein n is a positive integer comprising:
- a plurality of branches, each branch including:
- a summer circuit configured to add a feedback signal to a received input;
- a latch circuit configured to receive an output of the summer circuit, the latch circuit of each branch being driven on different phases of a clock signal to provide different partial bit sequences;
- and
- a feedback circuit including:
- a multiplexer configured to receive as input, the different partial bit sequences from the latch circuit of each branch, the multiplexer having a clocked select input and configured to multiplex the different partial bit sequences from the latch circuit of each branch to assemble a full rate bit sequence;
- and
- a filter configured to provide cancellation of intersymbol interference (ISI) on the received input using an output of the multiplexer, an output of the filter being provided to the summer circuit of each branch.
A method for decision feedback equalization, comprising:
- providing a 1/n rate decision feedback equalization circuit having a plurality of branches, wherein n is a positive integer;
- summing a feedback signal from one or more branches with a received input using a summer circuit;
- receiving an output of the summer circuit with a latch circuit, the latch circuit of each branch being driven on different phases of a clock signal to provide different partial bit sequences;
- feeding back an output of the latch circuit to a multiplexer which receives as input, the different partial bit sequences from the latch circuit of each branch, the multiplexer being configured to multiplex the different partial bit sequences from the latch circuit of each branch to assemble a full rate bit sequence;
- and
- canceling intersymbol interference (ISI) on the received input using a continuous-time infinite impulse response (IIR) filter with a frequency-domain transfer function, the filter receiving as input an output of the multiplexer and an output of the filter being provided to the summer circuit of each branch.
Dependencies are inferred from the claim text.