Data transfer system and associated products

A field programmable gate array comprising:

• a data consuming set chosen among a first data consuming set in a data transfer system and a second data consuming set in the data transfer system, and
• the data transfer system for transferring data signals between a system input and a system output, the data transfer system comprising:
• a transfer means for transferring the data signals from the first data consuming set to the second data consuming set, wherein:
• the first data consuming set is designed to receive the data signals from the system input, to write the data signals in the first data consuming set, and to read the data signals from the first data consuming set for sending the data signals towards a second data consuming set, and
• the second data consuming set is designed to receive the data signals from the first data consuming set, to write the data signals in the second data consuming set, and to read the data signals from the second data consuming set for sending the data signals to the system output, and wherein:
• said first data consuming set comprises a first FIFO memory storing said data signals for delaying the writing in said second data consuming set of said data signals read from said first data consuming set and said first data consuming set comprises a first Low Voltage Differential Signaling cell placed at the output of the first FIFO memory;
• said second data consuming set comprises a second FIFO memory storing said data signals for further delaying the writing in said second data consuming set of said data signals read from said first data consuming set, and a second Low Voltage Differential Signaling cell placed at the input of the second FIFO memory;
• the first data consuming set is designed to insert with the data signals to be transmitted to the second data consuming set a read request signal, said read request signal is a single bit signal which when set to ‘1’ triggers the reading of the data signals in the first FIFO memory, the transfer means are designed to carry the read request signal with the data signals through the first and second Low Voltage Differential Signaling cells, and the second data consuming set is designed to receive the read request signal which when set to ‘1’ triggers the writing of the data signals in the second FIFO memory;
• wherein said first data consuming set is designed to exploit a same first clock for writing said data signals in said first FIFO memory and for reading said data signals from said first FIFO memory, while said second data consuming set is designed to exploit a second writing clock for writing said data signals in said second FIFO memory and a second reading clock for reading said data signals from said second FIFO memory.

A non-transitory optical transmission component comprising:

• a data consuming set chosen among a first data consuming set in a data transfer system and a second data consuming set in the data transfer system, and
• the data transfer system for transferring data signals between a system input and a system output, the data transfer system comprising:
• a transfer means for transferring the data signals from the first data consuming set to the second data consuming set, wherein:
• the first data consuming set is designed to receive the data signals from the system input, to write the data signals in the first data consuming set, and to read the data signals from the first data consuming set for sending the data signals towards a second data consuming set, and
• the second data consuming set is designed to receive the data signals from the first data consuming set, to write the data signals in the second data consuming set, and to read the data signals from the second data consuming set for sending the data signals to the system output, and wherein:
• said first data consuming set comprises a first FIFO memory storing said data signals for delaying the writing in said second data consuming set of said data signals read from said first data consuming set and said first data consuming set comprises a first Low Voltage Differential Signaling cell placed at the output of the first FIFO memory;
• said second data consuming set comprises a second FIFO memory storing said data signals for further delaying the writing in said second data consuming set of said data signals read from said first data consuming set, and a second Low Voltage Differential Signaling cell placed at the input of the second FIFO memory;
• the first data consuming set is designed to insert with the data signals to be transmitted to the second data consuming set a read request, said read request signal is a single bit signal which when set to ‘1’ triggers the reading of the data signals in the first FIFO memory, the transfer means are designed to carry the read request signal with the data signals through the first and second Low Voltage Differential Signaling cells, and the second data consuming set is designed to receive the read request signal which when set to ‘1’ triggers the writing of said data signals in said second FIFO memory;
• wherein said first data consuming set is designed to exploit a same first clock for writing said data signals in said first FIFO memory and for reading said data signals from said first FIFO memory, while said second data consuming set is designed to exploit a second writing clock for writing said data signals in said second FIFO memory and a second reading clock for reading said data signals from said second FIFO memory.