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US 8,477,558 B2Granted
Memory apparatuses with low supply voltages
AssigneeIntel Corporation
InventorsJaume Abella, Xavier Vera, Javier Carretero Casado, Pedro Chaparro Monferrer, Antonio González
Life of this patent
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Abstract
Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.
Claims22
An apparatus comprising:
- a first memory including a first memory location;
- a memory controller including a read controller to prevent a read operation to the first memory location from being completed, for at least N clock cycles after a write operation to the first memory location, wherein N is the number of clock cycles for the first memory location to stabilize after the write operation;
- and
- a second memory to store at least M entries, an entry of the M entries comprising an address and data associated with the write operation, wherein M is based on a number of store instructions that commit per clock cycle and the N clock cycles.
1 more element
A method comprising:
- writing to a first memory location of a first memory;
- preventing reading the first memory location for at least N clock cycles after the writing to the first memory location, wherein N is the number of clock cycles for the first memory location to stabilize after the writing;
- and
- comparing an address of the first memory location to M number of address entries in a second memory, wherein M is based on a number of store instructions that commit per clock cycle and the N clock cycles.
1 more element
A processor comprising:
- an arithmetic logic unit to perform logic and arithmetic operations;
- an execution unit to execute instructions;
- a first memory including a first memory location;
- a memory controller including a read controller to prevent a read operation to the first memory location from being completed, for at least N clock cycles after a write operation to the first memory location, wherein N is the number of clock cycles for the first memory location to stabilize after the write operation.
1 more element
Dependencies are inferred from the claim text.