Input circuit of semiconductor memory apparatus and controlling method thereof
AssigneeSK hynix Inc.
InventorsYoung Ju Kim, Su Jeong Sim
Life of this patent
Estimating the term…
Abstract
Disclosed is an input circuit of a semiconductor memory apparatus. The input circuit includes a first buffer and a second buffer. The first buffer has an input terminal connected with a first input pin for receiving a control signal used in a multi-control mode for controlling an entire memory area by dividing the entire memory area, and an output terminal having a first level according to a control mode signal. The second buffer has an input terminal connected with a second input pin for receiving one of plural signals used in a single control mode for controlling the entire memory area without dividing the entire memory area, and an output terminal having a second level according to the control mode signal.
Claims17
An input circuit of a semiconductor memory apparatus, the input circuit comprising:
- a first input pin;
- a first buffer including an input terminal connected with the first input pin;
- a second input pin;
- and
- a second buffer including an input terminal connected with the second input pin, wherein
- one of the first buffer and the second buffer is activated and the other is inactivated in response to a control mode signal for determining a control scheme of the semiconductor memory apparatus.
An input circuit of a semiconductor memory apparatus, the input circuit comprising:
- a plurality of pins for receiving various signals including a control signal used in a multi-control mode for controlling a memory chip by dividing an entire memory area of the memory chip, and an address signal which is not used in the multi-control mode;
- and
- a plurality of buffers including input terminals connected with the pins, wherein
- first and second buffers of the buffers are connected with first and second pins for receiving the control signal and the address signal, and
- one of the first and second buffers is activated and the other is inactivated in response to a control mode signal for selecting the multi-control mode.
Dependencies are inferred from the claim text.