Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsHak-soo Yu, In-gyu Baek, Hong-sun Hwang, Young-kug Moon
Life of this patent
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Abstract
A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers.
Claims18
A semiconductor memory device comprising:
- a plurality of layers each comprising a memory cell array, the layers stacked over each other;
- at least one power plane for supplying power to the layers,
- wherein the at least one power plane includes a first region to which a power voltage is applied and a second region to which a ground voltage is applied, and
- wherein the first region is located adjacent to the second region, and the first and second regions form a decoupling capacitor there between to decouple an influx of power noise to the layers and decouple generation of power noise in the layers;
- a control layer that includes control logic for controlling access to the memory cell arrays of the layers;
- and
- a memory array driving circuit for driving the memory cell arrays of the layers.
A semiconductor memory device comprising:
- a plurality of layers each comprising a memory cell array, the layers stacked over each other;
- and
- at least one power plane for supplying power to the layers,
- wherein the at least one power plane includes a first region to which a power voltage is applied and a second region to which a ground voltage is applied,
- wherein the first region is located adjacent to the second region, and the first and second regions form a decoupling capacitor there between to decouple an influx of power noise to the layers and decouple generation of power noise in the layers, and
- wherein in the at least one power plane, the first region and the second region are in different layers.
A computing system including a semiconductor memory device comprising:
- a plurality of layers each comprising a memory cell array, the layers stacked over each other;
- at least one power plane for supplying power to the layers,
- wherein the at least one power plane comprises a first region to which a power voltage is applied and a second region to which a ground voltage is applied, and
- wherein the first region is located adjacent to the second region, and the first and second regions form a decoupling capacitor there between to decouple an influx of power noise to the layers and decouple generation of power noise in the layers;
- and
- a power line and a ground line through which the power voltage and the ground voltage are supplied to the power plane,
- the power line and the ground line are connected to a side or sides of the at least one power plane.
Dependencies are inferred from the claim text.