Pass-gated bump sense amplifier for embedded drams
AssigneeSTMicroelectronics International N.V.
InventorsShailendra Sharad, Rupak Kundu, G. Penaka Phani
Life of this patent
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Abstract
A sensing circuit for use in a semiconductor memory device includes first and second conducting lines for conducting a bit signal to and from a memory cell. The circuit further includes a sense amplifier coupled to the first and second conducting lines for sensing a bit signal, a charge storing element for generating a predefined potential, and first and second switching element respectively coupled to the first and second conducting lines. The first and second switching elements are selectively controllable to connect the first and second conducting line to the charge storing element so as to induce the generated predefined voltage on the first or second conducting lines.
Claims29
A sense circuit for use in a semiconductor memory device, the sense circuit comprising:
- a first and a second conducting line for conducting a bit signal from/to a memory cell;
- a sense amplifier coupled to the first and second conducting line, said sense amplifier being adapted to sense a bit signal;
- a charge storing element adapted to generate a predefined voltage;
- and
- a first and a second switching element respectively coupled to the first and second conducting lines, wherein:
- said first and second switching elements are selectively controllable to respectively couple the first and second conducting line to the charge storing element so as to induce the generated predefined voltage on the first or second conducting line and wherein the first and the second conducting line are pre-charged at ground.
A sense circuit for use in a semiconductor memory device, the sense circuit comprising:
- a first and a second conducting line for conducting a bit signal from/to a memory cell;
- a sense amplifier coupled to the first and second conducting lines, said sense amplifier being adapted to sense a bit signal;
- a charge storing element adapted to generate a predefined voltage;
- and
- a first and a second switching element respectively coupled to the first and second conducting lines, wherein:
- said first and second switching elements are selectively controllable to respectively couple the first and second conducting lines to the charge storing element so as to induce the generated predefined voltage on the first or second conducting line, wherein one of the first or second conducting lines is adapted to conduct a first signal and the remaining one of the first and second conducting lines is adapted to conduct a second complementary signal based on the generated predefined voltage, and wherein the first signal is non-zero and the second complementary signal is lower than the first signal.
A sense circuit for use in a semiconductor memory device, the sense circuit comprising:
- a first and a second conducting line for conducting a bit signal from/to a memory cell;
- a sense amplifier coupled to the first and second conducting lines, said sense amplifier being adapted to sense a bit signal;
- a charge storing element adapted to generate a predefined voltage;
- and
- a first and a second switching element respectively coupled to the first and second conducting lines, wherein:
- said first and second switching elements are selectively controllable to respectively couple the first and second conducting lines to the charge storing element so as to induce the generated predefined voltage on the first or second conducting line, wherein the first and second switching elements are adapted to be driven by a driving voltage corresponding to a high state of the memory cell, wherein the first and second switching elements are transistors, a gate of said transistors is selectively driven by the driving voltage, the source of said transistors is respectively coupled to the first and second connecting lines, and a drain of said transistors is coupled to the charge storing element, and wherein the first and second switching elements are n-channel transistors.
Dependencies are inferred from the claim text.