Semiconductor memory devices having redundancy arrays
AssigneeSamsung Electronics Co., Ltd.
InventorKye-hyun Kyung
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a plurality of memory areas. Each of the memory areas includes a normal cell array and a redundancy cell array for repairing defective cells generated in the normal cell array such that the semiconductor memory device is usable even when memory arrays include defective cells. A size of a redundancy cell array of a first memory area is greater than a size of the redundancy cell arrays of the other memory areas.
Claims21
A semiconductor memory device including a plurality of memory areas, each of the memory areas comprising:
- a normal cell array;
- and
- a redundancy cell array for repairing defective cells generated in the normal cell array,
- wherein the semiconductor memory device is configured to employ asymmetrical redundancy cell allocation by setting a ratio of a size of the redundancy cell array to a size of the normal cell array to be greater for a first memory area of the plurality of memory areas than for one or more second memory areas of the plurality of memory areas, such that a probability of repairing defective cells in the first memory area is increased with respect to the one or more second memory areas, and
- wherein the first memory area is configured to store system code, and the one or more second memory areas are configured to store data information.
A semiconductor memory device including a plurality of memory areas, the plurality of memory areas comprising:
- a first memory area including a first normal cell array and a first redundancy cell array, and configured to store information regarding system code;
- and
- a second memory area including a second normal cell array and a second redundancy cell array, and configured to store data information,
- wherein the semiconductor memory device is configured to employ asymmetrical redundancy cell allocation by setting a ratio of a size of the first redundancy cell array to a size of the first normal cell array of the first memory area to be greater than a ratio of a size of the second redundancy cell array to a size of the second normal cell array of the second memory area, such that a probability of repairing defective cells in the first memory area is increased with respect to the second memory area, and the second memory area is configured to store data information.
A semiconductor memory device comprising:
- one or more first memory areas configured to store system code, each of the first memory areas including a first normal cell array and a first redundancy cell array;
- one or more second memory areas configured to store data information, each of the second memory areas including a second normal cell array and a second redundancy cell array,
- wherein the semiconductor memory device is configured to employ asymmetrical redundancy cell allocation by setting a first ratio of a total size of the first redundancy cell array to a total size of the first normal cell array into be greater than a second ratio of a total size of the second redundancy cell array to a total size of the second normal cell array, such that a probability of repairing defective cells in the first memory area is increased with respect to the one or more second memory areas.
Dependencies are inferred from the claim text.