Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsHiroyuki Nagashima, Naoya Tokiwa
Life of this patent
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Abstract
A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.
Claims19
A semiconductor memory device, comprising:
- a silicon substrate;
- a plurality of memory layers arranged in multilayer, each memory layer including a cell array, said cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing said first lines, and a plurality of memory cells connected at intersections of said first lines and said second lines;
- a pulse generator operative to generate pulses required for data access to an access target memory cell in said plurality of memory cells;
- a control circuit operative to control said pulse generator such that the pulse output from said pulse generator has energy in accordance with the memory layer to which said access target memory cell belongs;
- and
- a current limiter operative to limit current flowing in said access target memory cell on access to said access target memory cell, wherein
- said control circuit controls said pulse generator based on the address of the access target memory cell and a parameter previously set at each of said plurality of memory layers.
A semiconductor memory device, comprising:
- a silicon substrate;
- a plurality of memory layers arranged in multilayer, each memory layer including a cell array, said cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing said first lines, and a plurality of memory cells connected at intersections of said first lines and said second lines;
- a pulse generator operative to generate pulses required for data access to said plurality of memory cells;
- and
- a control circuit operative to control said pulse generator such that the pulse output from said pulse generator has energy in accordance with the memory layer to which an access target memory cell belongs, wherein
- said pulse generator supplies plural pulses to said first or second lines in two or more of said plurality of memory layers, said plural pulses being different in step width at each memory layer.
Dependencies are inferred from the claim text.