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US 8,477,541 B2Granted
Semiconductor integrated circuit adapted to output pass/fail results of internal operations
AssigneeKabushiki Kaisha Toshiba
InventorsHiroshi Nakamura, Kenichi Imamiya, Toshio Yamamura, Koji Hosono, Koichi Kawai
Life of this patent
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Abstract
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
Claims32
A nonvolatile semiconductor memory device comprising:
- a plurality of memory cells or a plurality of memory cell units each including a plurality of memory cells;
- and
- a memory cell array including the plurality of memory cells or the plurality of memory cell units, being arranged to form an array;
- wherein a first operation is performed in response to an input of a first command or an input of a first command sequence, and after the input of the first command or the input of the first command sequence, a first ready/busy signal goes from a ready state to a busy state in a first timing, and then the first ready/busy signal goes from a busy state to a ready state in a second timing before the first operation is completed, and the first operation includes an operation in which data stored in a selected memory cell included in the plurality of memory cells or the plurality of memory cell units is changed from first data to second data;
- wherein a second operation is performed in response to an input of a second command or an input of a second command sequence, and after the input of the second command or the input of the second command sequence, the first ready/busy signal goes from a ready state to a busy state in a third timing, and then the first ready/busy signal is kept to a busy state until the first operation is completed, and the second operation includes an operation in which data stored in a selected memory cell included in the plurality of memory cells or the plurality of memory cell units is changed from the first data to the second data;
- and
- wherein the first command is different from the second command, the first command sequence is different from the second command sequence, and the first data is different from the second data.
4 more elements
A nonvolatile semiconductor memory device comprising:
- a plurality of memory cells or a plurality of memory cell units each including a plurality of memory cells;
- and
- a memory cell array including the plurality of memory cells or the plurality of memory cell units, being arranged to form an array;
- wherein a first operation including a first program operation is performed in response to an input of a first command, address input, data input, and an input of a second command, and after the input of the first command, the address input, the data input, and the input of the second command, a first ready/busy signal goes from a ready state to a busy state in a first timing, and then the first ready/busy signal goes from a busy state to a ready state in a second timing before the first operation is completed;
- wherein a second operation including a second program operation is performed in response to an input of a first command, address input, data input, and an input of a third command, and after the input of the first command, the address input, the data input, and the input of the third command, the first ready/busy signal goes from a ready state to a busy state in a third timing, and then the first ready/busy signal is kept to a busy state until the first operation is completed;
- and
- wherein the second command is different from the third command.
4 more elements
Dependencies are inferred from the claim text.