Static memory device with five transistors and operating method
AssigneeSTMicroelectronics (Tours) SAS
InventorsLahcen Hamouche, Jean-Christophe Lafont
Life of this patent
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Abstract
At the bottom of a column (COLi) of memory cells (CEL) of the SRAM type with five portless transistors, there is placed an additional cell (CLS), with a structure identical to the cells (CEL), which makes it possible to write and read a datum in a memory cell (CEL) of the column without using a read amplifier.
Claims17
An SRAM-type memory device, comprising:
- a memory plane having at least one column of memory cells of the SRAM type, each memory cell comprising two cross-coupled inverters and a single access transistor, each memory cell being connected between two bit lines, wherein the at least one column of the memory plane also comprises an additional memory cell, with a structure identical to that of the memory cells of said column, connected to the two bit lines, the two bit lines being configured to be powered by a power supply voltage;
- a controllable additional access means connected to said additional memory cell and having a first state to prevent access to said additional cell and a second state to allow access to said additional memory cell so as to store a datum therein or extract a datum therefrom;
- first control means configured to place said additional access means in said first or in said second state;
- and
- second control means configured to deliver, when the additional access means is in said first state, a first control signal to a gate of the access transistor of one of the memory cells of the column and a second control signal to a gate of the access transistor of the additional memory cell so as to place said memory cell in a read mode and the additional memory cell in a write mode, or vice versa.
An SRAM-type memory device, comprising:
- a memory plane having at least one column of memory cells of the SRAM type, wherein each memory cell is connected between two bit lines and comprises two cross-coupled inverters and a single access transistor, wherein the two bit lines are directly connected to the cross-coupled inverters of each memory cell and are configured to be powered by a power supply voltage;
- and
- control means configured to deliver a first control signal to the gate of the access transistor of a first memory cell of the column and a second control signal to the gate of the access transistor of a second memory cell of the column so as to concurrently place said first memory cell in a read mode and said second memory cell in a write mode, or vice versa.
A method of reading a datum from or writing a datum to a memory cell of a device, the memory cell being connected between two bit lines without access transistors between each of the two bit lines and the memory cell, the device including an additional memory cell with a structure identical to that of the memory cell and also being connected to the two bit lines and further including a memory access component and an additional memory access component, the method comprising:
- connecting the two bit lines to a power supply voltage;
- placing the additional memory access component of the additional memory cell in a first state;
- placing the memory cell in a read mode;
- placing the additional memory cell in a write mode;
- writing the opposite of the datum contained in said memory cell into said additional memory cell;
- placing the additional memory access component in a second state;
- and
- extracting said opposite datum from said additional memory cell.
A method of reading or writing a group of data contained in a selected line of memory cells of a block of a device having a memory plane of p blocks of m columns of n/p lines of memory cells, each memory cell being connected between two bit lines, each column including an additional memory cell, a second additional memory cell, an additional access component, two additional bit lines, a terminal additional memory cell, and a terminal additional access component, the method comprising:
- connecting the two bit lines of each column to a power supply voltage;
- placing additional access component of each additional memory cell of said block in a first state;
- placing each memory cell of said selected line in a read mode;
- placing each additional memory cell in a write mode, the opposite of the datum contained in each memory cell being written into the corresponding additional memory cell;
- placing said additional access component in a second state;
- connecting the two additional bit lines of each column to said power supply voltage;
- placing each additional memory cell of said block in a read mode;
- placing each second additional memory cell associated with said block in a write mode, the opposite of the datum contained in each additional memory cell being written into the corresponding second additional memory cell;
- placing said additional access component and the terminal additional access component in a first state;
- placing each second additional memory cell associated with said block in a read mode;
- placing each terminal additional memory cell in write mode, the opposite of the datum contained in each second additional memory cell being written into the corresponding terminal additional memory cell;
- and
- placing the terminal additional access component in a second state and extracting said datum contained in each terminal additional memory cell.
A method of copying the content of a first line of a memory plane into a second line of the memory plane, the memory plane having at least one column of memory cells of the SRAM type each memory cell comprising two cross-coupled inverters and a single access transistor, each memory cell being connected between two bit lines, and having a control component configured to deliver a first control signal to a gate of the access transistor of a first memory cell of the column and a second control signal to a gate of the access transistor of a second memory cell of the column, the method comprising:
- connecting the bit lines of each column to a power supply voltage;
- and
- placing the memory cells of a first line of the column in a read mode while placing the memory cells of a second line in the column in a write mode in response to the first and second control signals respectively.
Dependencies are inferred from the claim text.