Back to results
US 8,477,536 B2Granted
Method for manufacturing a semiconductor memory device
AssigneeElpida Memory, Inc.
InventorTakeshi Ohgami
Life of this patent
Estimating the term…
Abstract
A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.
Claims8
A method comprising:
- forming in a semiconductor body source and drain regions of a plurality of transistors constituting a select-line driving circuit that drives a select-line in response to selection information;
- forming an insulating layer over the semiconductor body including the source and drain regions;
- forming on the insulating layer a mask layer including a line-shaped opening such that the line-shaped opening is positioned over respective parts of the source and drain regions of the transistors with an intervention of the insulating layer;
- and
- forming a plurality of contact plugs each electrically connected to an associated one of the source and drain regions by use of a line SAC (Self-Align Contact) technique in which of the insulation layer is selectively removed by using the mask layer.
2 more elements
A method comprising:
- forming a plurality of gate structures on an active region in line, each of the gate structures comprising a gate electrode and an insulating film covering the gate electrode, the gate structures being respectively for a plurality of transistors each driving an associated one of word lines or column lines;
- forming interlayer insulating layer over the active region on which the gate structures are formed;
- forming a mask layer on the interlayer insulation layer, the mask layer having at least one opening, the opening being elongated to cross respective portions of the gate structures on the active region in which a plurality of contact holes for source and drain region of the transistors are to be formed;
- selectively removing the interlayer insulation layer by using the mask layer and the insulating film as a mask to form the contact holes;
- and
- forming contact plugs in the contact holes.
3 more elements
Dependencies are inferred from the claim text.