SRAM timing cell apparatus and methods

An integrated circuit comprising:

• user defined circuitry formed on a semiconductor substrate;
• and
• an embedded SRAM circuit formed on the semiconductor substrate, the embedded SRAM circuit further comprising:
• an SRAM array comprising static random access memory cells arranged in rows and columns;
• a plurality of word lines each coupled to memory cells along one of the rows;
• a plurality of true and complement bit line pairs, each bit line pair coupled to memory cells along one of the columns;
• sense amplifiers coupled to one of the true and complement bit line pairs for sensing a differential voltage on the bit line pair;
• a clock generation circuit for outputting clock signals;
• a word line generation circuit for generating a word line pulse on at least one of the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals;
• and
• a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time;
• wherein the tracking cell further comprises SRAM tracking circuits, each having an input and an output and positioned in the SRAM array and coupled in series to provide a signal indicative of the SRAM tracking time.

A method, comprising:

• providing an SRAM array comprising a plurality of SRAM bit cells arranged in rows and columns;
• coupling a plurality of word lines to SRAM bit cells arranged along rows of the SRAM array;
• coupling a plurality of bit line pairs to SRAM bit cells arranged in columns of the SRAM array;
• coupling sense amplifiers to each of the bit line pairs to sense s differential voltage developed between the bit line pairs during an SRAM read operation;
• providing an SRAM tracking cell comprising a plurality of SRAM tracking circuits disposed within the SRAM array, each having an input and an output and coupled in series;
• and importing a clock to an SRAM tracking circuit and outputting a word line pulse end signal following an SRAM tracking time.