Nonvolatile semiconductor memory and manufacturing method of nonvolatile semiconductor memory
AssigneeKabushiki Kaisha Toshiba
InventorHiroshi Ito
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a nonvolatile semiconductor memory includes word lines, bit lines, memory cells, a dummy word line, a dummy bit line and dummy cells. The word lines and the bit lines cross. The memory cells are provided for each intersection of the word lines and bit lines. Each memory cell includes a first diode and a resistance change memory element. The dummy word line crosses the bit lines. The dummy bit line crosses the word lines. The dummy cells are provided at each intersection of the dummy word line and the bit lines, and at each intersection of the dummy bit line and the word lines. Each dummy cell includes a second diode.
Claims18
A nonvolatile semiconductor memory comprising:
- word lines;
- bit lines crossing the word lines;
- memory cells, which are provided for each intersection of the word lines and bit lines, each memory cell including a first diode and a resistance change memory element;
- a dummy word line crossing the bit lines;
- a dummy bit line crossing the word lines;
- dummy cells which are provided at each intersection of the dummy word line and the bit lines, and at each intersection of the dummy bit line and the word lines, each dummy cell including a second diode;
- and
- a driving unit which sets the dummy word line and dummy bit line to a selected state, sets the word lines and bit lines to an unselected state, and biases the word lines and bit lines through the second diodes of the dummy cells, as a stand-by state.
A nonvolatile semiconductor memory comprising:
- word lines;
- bit lines crossing the word lines;
- memory cells, which are provided for each intersection of the word lines and bit lines, each memory cell including a first diode and a resistance change memory element;
- a dummy word line crossing the bit lines;
- a dummy bit line crossing the word lines,
- dummy cells which are provided at each intersection of the dummy word line and the bit lines, and at each intersection of the dummy bit line and the word lines, each dummy cell including a second diode;
- and
- an insulation unit provided at an intersection of the dummy word line and dummy bit line.
Dependencies are inferred from the claim text.