US 8,477,522 B2 · Ferroelectric memory write-back

Abstract

A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.

Claims13

Dependent claims

A method of operating a ferroelectric memory device, the method comprising:

biasing a ferroelectric capacitor to a first state by applying a voltage across the ferroelectric capacitor and removing the voltage;
reading a first state from the ferroelectric capacitor via a bit line electrically connected to the ferroelectric capacitor through a switch;
in response to signal amplification on the bit line during reading the first state, activating a global bit line that in response activates a buffer electrically coupled to the global bit line, the buffer having an output electrically coupled to the bit line;
wherein the buffer is electrically coupled to a write line and is configured to output to the bit line a signal derived from the global bit line based on an input received from the write line;
wherein reading the first state comprises:
activating a word line and a compliment word line;
after activating the word line and the compliment word line, pulsing a plate line electrically coupled to the ferroelectric capacitor;
and
after pulsing the plate line, activating a sense amplifier electrically coupled to the bit line and bit line compliment.

6 more elements

A ferroelectric memory apparatus comprising:

a bit cell comprising:
a ferroelectric capacitor electrically coupled to a plate line, and
a switch coupled between the ferroelectric capacitor and a bit line, the switch controlled at least in part by a word line;
a sense amplifier electrically coupled to the bit line;
a read buffer configured to apply a voltage to a global bit line in response to signal amplification of the bit line during reading of the bit cell and a signal received from a read line coupled to the read buffer;
a tri-state buffer comprising:
an input electrically coupled to the global bit line,
an output electrically coupled to the bit line and configured to output a signal derived from the global bit line to the bit line,
a control input electrically coupled to a write line to receive a signal regarding the signal to pass to the bit line for writing data to the bit cell.

6 more elements

Dependencies are inferred from the claim text.

Ferroelectric memory write-back

Life of this patent

Ferroelectric memory write-back

Life of this patent

Abstract

Claims13