Semiconductor memory device
AssigneeElpida Memory, Inc.
InventorsYuki Hosoe, Kazuki Ishizuka
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a first amplifier circuit, a second amplifier circuit, first and second bit lines coupled to the first amplifier circuit, third and fourth bit lines coupled to the second amplifier circuit, a first equalizer circuit being coupled to the first and second bit lines, and a second equalizer circuit being coupled between the second and third bit lines. The second equalizer circuit being closer to the second amplifier circuit than the first equalizer circuit, the first equalizer circuit being closer to the first amplifier circuit than the second equalizer circuit.
Claims9
A semiconductor device comprising:
- first and second amplifier circuits;
- first and second bit lines each coupled to the first amplifier circuit, the first bit line extending from the first amplifier circuit in a first direction and the second bit line extending from the first amplifier circuit in a second direction opposite the first direction;
- third and fourth bit lines coupled to the second amplifier circuit extending from the second amplifier circuit, the third bit line extending parallel to the first bit line, the third bit line extending from the second amplifier circuit in the second direction and the fourth bit line extending from the second amplifier circuit in the first direction;
- a first equalizer circuit coupled between the first bit line and the second bit line;
- and
- a second equalizer circuit coupled between the first bit line and the third bit line.
A semiconductor device comprising:
- first and second amplifier circuits;
- first and second bit lines each coupled to the first amplifier circuit, the first bit line extending from the first amplifier circuit and the second bit line extending to an opposite side to the first bit line with respect to the first amplifier circuit;
- third and fourth bit lines coupled to the second amplifier circuit, the third and fourth bit lines extending from the second amplifier circuit and the fourth bit line extending to opposite side to the third bit line with respect to the second amplifier circuit;
- a first equalizer circuit coupled between the first bit line and the second bit line;
- a second equalizer circuit coupled between the first bit line and the third bit line;
- a third equalizer circuit coupled between the one end of the third bit line and the one end of the fourth bit line;
- a fourth equalizer circuit coupled between the one end of the first bit line and the other end of the third bit line;
- first and second areas;
- and
- a first memory cell mat sandwiched between the first and second areas, the first and second areas and the first memory cell mat being arranged in a first direction in which the bit lines extend,
- wherein the first and second amplifier circuits are disposed respectively on the first and second areas, and
- wherein the third equalizer circuit is disposed on the second area and the fourth equalizer circuit is disposed on the first area.
Dependencies are inferred from the claim text.