Method and apparatus to limit maximum switch current in a switching power supply

An integrated circuit for use in a power supply, the integrated circuit comprising:

• a drive signal generator configured to generate a drive signal in response to a clock signal to control switching of a switch included in the power supply;
• a first delay coupled to receive the drive signal and to generate a first delayed drive signal that is delayed by a leading edge blanking time;
• a second delay coupled to receive the first delayed drive signal and to generate a second delayed drive signal that is further delayed by a current limit delay time;
• a comparator coupled to detect whether a switch current through the switch exceeds a current limit;
• a first logic coupled to receive an output of the comparator and the first delayed drive signal, wherein the first logic generates an over current signal indicating that the switch current exceeds the current limit after the leading edge blanking time;
• a first short on time detector coupled to receive the over current signal, the second delayed drive signal, and a signal indicating whether the switch is on, wherein the first short on time detector sets a first latch indicating that an on time of the switch is a short on time if the switch current exceeds the current limit after a sum of the leading edge blanking time and the current limit delay time;
• and
• a second logic coupled to receive the drive signal and the second delayed drive signal to detect long pulses of the drive signal, wherein the second logic is coupled to reset the first latch indicating that the on time of the switch is not a short on time if the on time of the switch is greater than a sum of the leading edge blanking period and the current limit delay time period.