Method and apparatus for monitoring mask process impact on lithography performance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPing Chieh Wu, Chien-Hsun Chen, Ru-Gun Liu, Wen-Chun Huang, Chih-Ming Lai, Boren Luo
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Abstract
The present disclosure is directed generally to a method and apparatus for monitoring mask process impact on lithography performance. A method including receiving a physical wafer pattern according to a mask, extracting a mask contour from the mask, and extracting a deconvolution pattern based on the mask contour. A lithography process is simulated to create a virtual wafer pattern based on the deconvolution pattern. The virtual wafer pattern is then compared to the physical wafer pattern.
Claims20
A method, comprising:
- receiving a physical wafer pattern according to a mask;
- extracting a mask contour from the mask;
- extracting a deconvolution pattern based on the mask contour;
- simulating a lithography process to create a virtual wafer pattern based on the deconvolution pattern;
- and
- comparing the virtual wafer pattern and the physical wafer pattern.
A method, comprising:
- extracting a mask contour from a mask layout;
- extracting a deconvolution pattern based on the mask contour;
- analyzing the deconvolution pattern;
- performing a failure mode analysis according to the analyzing;
- receiving first pattern data from a physical device patterned according to the mask layout;
- and
- receiving second pattern data from the deconvolution pattern;
- wherein, analyzing the deconvolution pattern includes comparing the first pattern data from the second pattern data.
An apparatus, having a computer-readable medium, the computer-readable medium having instructions executable by a processor, comprising:
- instructions that extract a mask contour from a mask based on a design pattern;
- instructions that extract a deconvolution pattern based on the mask contour;
- instructions that simulate a mask process to create a virtual mask contour based on the deconvolution pattern;
- instructions that simulate a lithography process to create a virtual wafer pattern based on the virtual mask contour;
- instructions for receiving a physical wafer pattern, wherein the physical wafer pattern is from a wafer that has been processed using the mask and a fabrication process;
- and
- instructions that compare the virtual wafer pattern and the physical wafer pattern for failure analysis.
Dependencies are inferred from the claim text.