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US 8,477,220 B2Granted
Solid-state image pickup device
AssigneeOlympus Corporation
InventorsSusumu Yamazaki, Yoshio Hagihara
Life of this patent
Estimating the term…
Abstract
A solid state image pickup device may include a pixel unit that includes a plurality of pixels; a pulse delay unit that includes a plurality of delay elements, each of the plurality of delay elements including a power supply terminal; a stop control unit; a stop signal delay unit; a lower bit latch unit; a counter unit; a first upper bit latch unit; a second upper bit latch unit; and a correcting unit that compares an output signal of the first upper bit latch unit with an output signal of the second upper bit latch unit, and corrects a count value, which is a count result of the counter unit, based on a comparison result and an output signal of the lower bit latch unit.
Claims12
A solid state image pickup device comprising:
- a pixel unit that includes a plurality of pixels arranged in the form of a matrix, each of the plurality of pixels generating a pixel signal, the pixel signal being output from a plurality of pixel signal output lines arranged to correspond to a column of the plurality of pixels;
- a pulse delay unit that includes a plurality of delay elements connected in a ring form, each of the plurality of delay elements including a power supply terminal that is connected to one of the plurality of pixel signal output lines, one of the plurality of delay elements including an input terminal that receives a pulse, each of the plurality of delay elements transferring the pulse with a delay time corresponding to the pixel signal;
- a stop control unit that outputs a stop signal when a predetermined time elapses after the pulse delay unit receives the pulse;
- a stop signal delay unit that outputs a delay stop signal delayed from the stop signal;
- a lower bit latch unit that latches output signals of the plurality of delay elements when receiving the delay stop signal;
- a counter unit that counts a circulation number of the pulse based on an output signal of one of the plurality of delay elements;
- a first upper bit latch unit that latches at least a least significant bit of an output signal of the counter unit when receiving the delay stop signal;
- a second upper bit latch unit that latches the output signal of the counter unit when receiving the delay stop signal;
- and
- a correcting unit that compares an output signal of the first upper bit latch unit with an output signal of the second upper bit latch unit, and corrects a count value, which is a count result of the counter unit, based on a comparison result and an output signal of the lower bit latch unit.
7 more elements
A solid state image pickup device comprising:
- a pixel unit that includes a plurality of pixels arranged in the form of a matrix, each of the plurality of pixels generating a pixel signal, the pixel signal being output from a plurality of pixel signal output lines arranged to correspond to a column of the plurality of pixels;
- a pulse delay unit that includes a plurality of delay elements connected in a ring form, each of the plurality of delay elements including a power supply terminal that is connected to one of the plurality of pixel signal output lines, one of the plurality of delay elements including an input terminal that receives a pulse, each of the plurality of delay elements transferring the pulse with a delay time corresponding to the pixel signal;
- a stop control unit that outputs a stop signal when a predetermined time elapses after the pulse delay unit receives the pulse;
- a stop signal delay unit that outputs a first delay stop signal delayed from the stop signal and a second delay stop signal delayed from the first delay stop signal;
- a lower bit latch unit that latches output signals of the plurality of delay elements when receiving the first delay stop signal;
- a first counter/latch unit that counts a circulation number of the pulse based on an output signal of one of the plurality of delay elements, and latches the circulation number when receiving the first delay stop signal;
- a second counter/latch unit that is smaller in the number of bits than the first counter/latch unit, counts a circulation number of the pulse based on an output signal of one of the plurality of delay elements, and latches the circulation number when receiving the stop signal;
- a third counter/latch unit that is smaller in the number of bits than the first counter/latch unit, counts a circulation number of the pulse based on an output signal of one of the plurality of delay elements, and latches the circulation number when receiving the second delay stop signal;
- and
- a correcting unit that compares an output signal of the first counter/latch unit, an output signal of the second counter/latch unit, and an output signal of the third counter/latch unit, and corrects a count value, which is a count result of the first counter/latch unit, based on a comparison result and an output signal of the lower bit latch unit.
7 more elements
A solid state image pickup device comprising:
- a pixel unit that includes a plurality of pixels arranged in the form of a matrix, each of the plurality of pixels generating a pixel signal, the pixel signal being output from a plurality of pixel signal output lines arranged to correspond to a column of the plurality of pixels;
- a pulse delay unit that includes a plurality of delay elements connected in a ring form, each of the plurality of delay elements including a power supply terminal that is connected to one of the plurality of pixel signal output lines, one of the plurality of delay elements including an input terminal that receives a pulse, each of the plurality of delay elements transferring the pulse with a delay time corresponding to the pixel signal;
- a stop control unit that outputs a stop signal when a predetermined time elapses after the pulse delay unit receives the pulse;
- a stop signal delay unit that outputs a first delay stop signal delayed from the stop signal and a second delay stop signal delayed from the first delay stop signal;
- a lower bit latch unit that latches output signals of the plurality of delay elements when receiving the first delay stop signal;
- a first counter/latch unit that counts a circulation number of the pulse based on an output signal of one of the plurality of delay elements, and latches the circulation number when receiving the second delay stop signal;
- a second counter/latch unit that is smaller in the number of bits than the first counter/latch unit, counts a circulation number of the pulse based on an output signal of one of the plurality of delay elements, and latches the circulation number when receiving the stop signal;
- a correcting unit that compares an output signal of the first counter/latch unit with an output signal of the second counter/latch unit, and corrects a count value, which is a count result of the first counter/latch unit, based on a comparison result and an output signal of the lower bit latch unit.
5 more elements
Dependencies are inferred from the claim text.