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US 8,477,094 B2Granted
Shift register and display device using the same
AssigneeLG Display Co., Ltd.
InventorsShanghoon Jung, Juhnsuk Yoo
Life of this patent
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Abstract
A shift register comprises a plurality of stages, which includes a (n−3)-th (where n is a positive integer) stage to a (n+3)-th stage, supplied with gate shift clocks which are sequentially delayed, a forward gate start pulse, a reverse gate start pulse, a carry signal, a gate high voltage, and a gate low voltage lower than the gate high voltage, and connected to each other in cascade, wherein the n-th stage, supplied with a (n−1)-th gate shift clock, an n-th gate shift clock, and a (n+1)-th gate shift clock, includes a scan pulse output unit, a carry signal output unit, and a shift direction changing switch circuit.
Claims18
A shift register comprising:
- a plurality of stages, which includes a (n−3)-th (where n is a positive integer) stage to a (n+3)-th stage, supplied with gate shift clocks that are sequentially delayed, a forward gate start pulse, a reverse gate start pulse, a carry signal, a gate high voltage, and a gate low voltage lower than the gate high voltage, and connected to each other in cascade,
- wherein the n-th stage, supplied with a (n−1)-th gate shift clock, an n-th gate shift clock, and a (n+1)-th gate shift clock, includes:
- a scan pulse output unit configured to output an n-th scan pulse depending on a voltage at a Q node via a first output node;
- a carry signal output unit configured to output an n-th carry signal depending on a voltage at the Q node via a second output node separated from the first output node;
- and
- a shift direction changing switch circuit configured to charge the Q node in response to a (n−3)-th carry signal output from the (n−3)-th stage, in a forward shift mode where the forward gate start pulse is generated, and, to charge the Q node in response to a (n+3)-th carry signal output from the (n+3)-th stage, in a reverse shift mode where the reverse gate start pulse is generated,
- wherein the n-th stage further comprises a Q node voltage maintaining switch circuit configured to charge the Q node in response to the (n−1)-th gate shift clock in the forward shift mode, and to charge the Q node in response to the (n+1)-th gate shift clock in the reverse shift mode.
4 more elements
A display device comprising:
- a display panel provided with a plurality of data lines and scan lines intersecting each other, and a plurality of pixels arranged in a matrix;
- a data driving circuit configured to supply data voltages for the data lines;
- and
- a scan driving circuit configured to sequentially supply scan pulses for the scan lines,
- wherein the scan driving circuit has a plurality of stages, which includes a (n−3)-th (where n is a positive integer) stage to a (n+3)-th stage, supplied with gate shift clocks that are sequentially delayed, a forward gate start pulse, a reverse gate start pulse, a carry signal, a gate high voltage, and a gate low voltage lower than the gate high voltage, and connected to each other in cascade, and
- wherein the n-th stage, supplied with a (n−1)-th gate shift clock, an n-th gate shift clock, and a (n+1)-th gate shift clock, includes:
- a scan pulse output unit configured to output an n-th scan pulse depending on a voltage at a Q node via a first output node;
- a carry signal output unit configured to output an n-th carry signal depending on a voltage at the Q node via a second output node separated from the first output node;
- and
- a shift direction changing switch circuit configured to charge the Q node in response to a (n−3)-th carry signal output from the (n−3)-th stage, in a forward shift mode where the forward gate start pulse is generated, and, to charge the Q node in response to a (n+3)-th carry signal output from the (n+3)-th stage, in a reverse shift mode where the reverse gate start pulse is generated,
- wherein the n-th stage further comprises a Q node voltage maintaining switch circuit configured to charge the Q node in response to the (n−1)-th gate shift clock in the forward shift mode, and to charge the Q node in response to the (n+1)-th gate shift clock in the reverse shift mode.
8 more elements
Dependencies are inferred from the claim text.