Method, system, and apparatus for interpolating an output of an analog-to-digital converter

An apparatus, comprising:

• an analog-to-digital converter (ADC) circuit configured to receive an input signal and sample the input signal at a sampling rate to supply a first plurality of samples of first data at a first data rate;
• a circuit configured to receive the first plurality of samples of the first data at the first data rate and supply a plurality of samples of second data at a second data rate, the second data rate being less than the first data rate;
• a digital signal processor, a portion of which being configured to receive the plurality of samples of the second data at the second data rate;
• a clock circuit configured to generate a first clock signal;
• and
• a clock divider circuit, which receives the first clock signal, the clock divider circuit being configured to output a second clock signal in response to the first clock signal;
• wherein the circuit configured to receive the first plurality of samples receives the first plurality of samples of the first data at the first data rate in response to the first clock signal;
• and
• wherein the circuit supplies the plurality of samples of second data at the second data rate in response to the second clock signal.

A system, comprising:

• a transmitter configured to output an optical signal;
• a photodiode configured to receive a portion of the optical signal and generate an electrical signal in response thereto;
• an analog-to-digital converter (ADC) circuit supplying a first plurality of samples of first data at a first data rate based, at least in part, on the electrical signal;
• a circuit configured to receive the first plurality of samples of the first data and supply a plurality of samples of second data at a second data rate, the second data rate being less than the first data rate;
• a digital signal processor, a portion of which being configured to receive the plurality of samples of the second data at the second data rate, the second data rate being less than the first data rate;
• and
• a plurality of transmitters, each of which supplying a corresponding one of a plurality of optical signals, the transmitter being one of the plurality of transmitters and the optical signals being one of the plurality of optical signals, each of the plurality of optical signals having a corresponding one of a plurality of wavelengths.

An apparatus, comprising:

• an analog-to-digital converter (ADC) circuit configured to receive an input signal and sample the input signal at a sampling rate to supply a first plurality of samples of first data at a first data rate;
• and
• a digital signal processor including:
• a circuit configured to receive the first plurality of samples of the first data at the first data rate and supply a plurality of samples of second data at a second data rate, the second data rate being less than the first data rate;
• and
• a portion configured to receive the plurality of samples of the second data at the second data rate,
• wherein the circuit configured to receive the first plurality of samples includes:
• a memory configured to receive the first plurality of samples of the first data at the first data rate and output a second plurality of samples of the first data at a second data rate less than the first data rate;
• and
• a filter circuit configured to receive the second plurality of samples of the first data from the memory at the second data rate and supply a plurality of samples of second data at a second data rate.

An apparatus, comprising:

• an analog-to-digital converter (ADC) circuit configured to receive an input signal and sample the input signal at a sampling rate to supply a plurality of samples of first data at a first data rate;
• a filter circuit configured to receive the plurality of samples of the first data at the first data rate and supply a first plurality of samples of second data at the first data rate;
• a memory circuit configured to receive the first plurality of samples of the second data at the first data rate and having circuitry to supply a second plurality of samples of the second data at a second data rate less than the first data rate;
• and
• a digital signal processor, a portion of which being configured to receive the second plurality of samples of second data at the second data rate.

An apparatus, comprising:

• an analog-to-digital converter (ADC) circuit configured to receive an input signal and sample the input signal at a sampling rate to supply a first plurality of samples of first data at a first data rate;
• a memory configured to receive the first plurality of samples of the first data at the first data rate and having circuitry to output a second plurality of samples of the first data at a second data rate less than the first data rate;
• a filter circuit configured to receive the second plurality of samples of the first data from the memory at the second data rate and supply a plurality of samples of second data at the second data rate;
• and
• a digital signal processor, a portion of which being configured to receive the plurality of samples of second data at the second data rate,
• wherein each of the first plurality of samples of the first data includes a first number of bits, each of the second plurality of samples of the first data includes a second number of bits, and each of the plurality of samples of the second data includes a third number of bits, the first number of bits being different than the second number of bits, and the first number of bits being different than the third number of bits.