Method and apparatus for self-test of successive approximation register (SAR) A/D converter

A method for testing an analog to digital converter (ADC), the ADC including a capacitor array, wherein the capacitor array includes one or more binary weighted capacitors and an additional capacitor, the method comprising:

• selecting one of the binary weighted capacitors as a test capacitor;
• applying a first voltage to the first plate of the additional capacitor and the capacitors of the capacitor array that have capacitance less than the capacitance of the test capacitor;
• applying a second voltage to the first plate of the remaining capacitors of the capacitor array, wherein the remaining capacitors comprise the capacitor under test and the capacitors that have a capacitance greater than the capacitance of the capacitor under test;
• switching off the connection to a second plate of the one of more binary weighted capacitors;
• applying the first voltage to the capacitor under test and applying the second voltage to the capacitors that have capacitance less than the capacitance of the capacitor under test and the additional capacitor;
• running successive approximation to measure a binary code that corresponds to the generated residue voltage by the capacitor array, wherein the binary code represents the error in the value of the test capacitor;
• and
• comparing the binary code with a predetermined value to generate an ADC status signal, wherein the ADC status signal indicates at least one of a pass status or fail status of the ADC.