Method and apparatus for amplifying a time difference

A time amplifier circuit comprising:

• a first inverter comprising a first NMOS transistor and a first PMOS transistor, respective gates of the first NMOS and PMOS transistors coupled together to a first input node for receiving a first input signal, respective drains of the first NMOS and PMOS transistors coupled together to provide a first output signal at a first output node, a source of the first PMOS transistor coupled to a power supply node through a first additional PMOS transistor having a gate coupled to the first input node;
• a second inverter comprising a second NMOS transistor and a second PMOS transistor, respective gates of the second NMOS transistor and the second PMOS transistor coupled together to a second input node for receiving a second input signal, respective drains of the second NMOS transistor and the second PMOS transistor coupled together to provide a second output signal at a second output node, a source of the second PMOS transistor coupled to the power supply node through a second additional PMOS transistor having a gate coupled to the second input node;
• a first pull-up path, from the first output node to the power supply node, enabled in response to the first input signal and the second output signal being low;
• and
• a second pull-up path, from the second output node to the power supply node, enabled in response to the second input signal and the first output signal being low;
• wherein the voltage at the first input node is independent of the voltage at the second input node.

A method of amplifying a time difference between rising edges of two signals, the method comprising:

• receiving a first input signal and a second input signal;
• inverting the first signal to provide a first output signal at a first output node;
• inverting the second input signal to provide a second output signal at a second output node;
• providing a first independent pull-down path from the first output node to a ground node through two or more NMOS transistors biased by the first input signal, wherein the first independent pull-down path is provided independent of a voltage at the second output node;
• providing a second independent pull-down path from the second output node to the ground node through two or more NMOS transistors biased by the second input signal, wherein the second independent pull-down path is provided independent of a voltage at the first output node;
• enabling a first dependent pull-down path from the first output node to the ground node in response to a first condition being met;
• and
• enabling a second dependent pull-down path from the second output node to the ground node in response to a second condition being mets,
• wherein the first input signal is independent of the second input signal;
• and wherein the first condition is that the first input signal and the second output signal are high, and the second condition is that the second input signal and the first output signal are high.

A time amplifier circuit comprising:

• a first inverter comprising a first NMOS transistor and a first PMOS transistor, respective gates of the first NMOS and PMOS transistors coupled together to a first input node for receiving a first input signal, respective drains of the first NMOS and PMOS transistors coupled together by a first output node to provide a first output signal at the first output node, a source of the first NMOS transistor coupled directly to a ground node;
• a second inverter comprising a second NMOS transistor and a second PMOS transistor, respective gates of the second NMOS transistor and the second PMOS transistor coupled together to a second input node for receiving a second input signal, respective drains of the second NMOS transistor and the second PMOS transistor coupled together by a second output node to provide a second output signal at the second output node, a source of the second NMOS transistor coupled directly to the ground node;
• a first pull-down path, from the first output node to the ground node, enabled in response to the first input signal and the second output signal being high;
• and
• a second pull-down path, from the second output node to ground, enabled in response to the second input signal and the first output signal being high;
• wherein the voltage at the first input node is independent of the voltage at the second input node.

A time amplifier circuit comprising:

• a first inverter comprising a first NMOS transistor and a first PMOS transistor, respective gates of the first NMOS and PMOS transistors coupled together to a first input node for receiving a first input signal, respective drains of the first NMOS and PMOS transistors coupled together to provide a first output signal at a first output node, a source of the first PMOS transistor coupled directly to a power supply node;
• a second inverter comprising a second NMOS transistor and a second PMOS transistor, respective gates of the second NMOS transistor and the second PMOS transistor coupled together to a second input node for receiving a second input signal, respective drains of the second NMOS transistor and the second PMOS transistor coupled together to provide a second output signal at a second output node, a source of the second PMOS transistor coupled directly to the power supply node;
• a first pull-up path, from the first output node to the power supply node, enabled in response to the first input signal and the second output signal being low;
• and
• a second pull-up path, from the second output node to the power supply node, enabled in response to the second input signal and the first output signal being low;
• wherein the voltage at the first input node is independent of the voltage at the second input node.

A method of amplifying a time difference between rising edges of two signals, the method comprising:

• receiving a first input signal and a second input signal;
• inverting the first signal to provide a first output signal at a first output node;
• inverting the second input signal to provide a second output signal at a second output node;
• providing a first independent pull-down path from the first output node to a ground node through exactly one NMOS transistor, wherein the first independent pull-down path is provided independent of a voltage at the second output node;
• providing a second independent pull-down path from the second output node to the ground node through exactly one NMOS transistor, wherein the second independent pull-down path is provided independent of a voltage at the first output node;
• enabling a first dependent pull-down path from the first output node to the ground node in response to a first condition being met, wherein the first dependent pull-down path is dependent on a signal at the second output node and the first dependent pull-down path includes an NMOS transistor having a gate driven by the first input signal;
• and
• enabling a second dependent pull-down path from the second output node to the ground node in response to a second condition being met, wherein the second dependent pull-down path is dependent on a signal at the first output node and the second dependent pull-down path includes an NMOS transistor having a gate driven by the second input signal.