3D integrated circuit stack-wide synchronization circuit

A method for providing a stack-wide synchronous signal to each stratum of a 3D chip stack having multiple circuits and two or more strata interconnected using at least a first and a second connection chain, each of the first and the second connection chains being in a stack-wide broadcast configuration, the method comprising:

• providing on each of the two or more strata:
• a synchronizer, connected to the first connection chain, configured to receive an asynchronous signal therefrom and perform a synchronization of the asynchronous signal to a clock signal to provide a synchronous signal with respect to the clock signal;
• a driver, connected to the second connection chain, configured to drive the synchronous signal;
• and
• a latch, connected to the second connection chain, configured to receive the synchronous signal driven by the driver on a same one of a different one of the two or more strata within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to at least one of the multiple circuits on a same one of the two or more strata,
• wherein the method comprises configuring the driver on each of the two or more strata such that an output of a single driver on one of the two or more strata is selected at any given time for use by the latch on all of the two or more strata.

A method for providing a stack-wide synchronous signal to each stratum of a 3D chip stack having multiple circuits and two or more strata interconnected using at least a first and a second connection chain, each of the first and the second connection chains being in a stack-wide broadcast configuration, the method comprising:

• with respect to each of the two or more strata:
• receiving an asynchronous signal;
• performing a synchronization of the asynchronous signal to a clock signal to provide a synchronous signal with respect to the clock signal;
• receiving the synchronous signal driven by a driver on a same one or a different one of the two or more strata;
• and
• latching the synchronous signal within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to at least one of the multiple circuits on a same one of the two or more strata,
• wherein a driver is provided on each of the two or more strata and is configured such that an output of a single driver on one of the two or more strata is selected at any given time to provide the synchronous signal on each of the two or more strata for said step of receiving the synchronous signal.

A stack-wide synchronization circuit for synchronizing an asynchronous signal in each stratum of a 3D chip stack having two or more strata interconnected using at least a first and a second chain of vias, each of the first and the second chain of vias being in a stack-wide broadcast configuration, the stack-wide synchronization circuit comprising, on each of the two or more strata:

• a first connection point for receiving the asynchronous signal;
• an off-chip receiver having an input and an output, the input connected to the connection point;
• an asynchronous-to-synchronous signal converter having an input connected to an output of the off-chip receiver;
• a tri-state driver having a non-selection input connected an output of the asynchronous-to-synchronous signal converter;
• a second connection point, connected to an output of the tri-state driver;
• an inter-strata receiver having an input connected to the second connection point;
• and
• a staging latch having an input connected to an output of the inter-strata receiver,
• wherein the first connection point is connected to the first chain of vias and the second connection point is connected to the second chain of vias, the tri-state drivers are configured such that an output of a single tri-state driver on one of the two or more strata is selected at any given time, and wherein the output of the staging latch on each of the two or more strata provides a stack-wide synchronous signal during a given clock cycle responsive to a receipt of the asynchronous input signal by the first connection point on any of the two or more strata during an immediately preceding clock cycle with respect to the given clock cycle.