High-speed latch circuit
AssigneeIPGoal Microelectronics (SiChuan) Co., Ltd.
InventorsYong Quan, Guosheng Wu
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Abstract
A high-speed latch circuit includes a latching unit for latching an inputted signal, a signal input unit connected to the latching unit and a clock control unit connected to the signal input unit. The clock control unit includes a first switch element, a second switch element connected to the first switch element and an inverter connected to the second switch element. The first switch element and the inverter are both connected to a clock signal input end. The high-speed latch circuit of the present invention has a simple circuit structure, shortens the triggering time of the signal and reduces chances of wrong triggering.
Claims9
A high-speed latch circuit, comprising a latching unit for latching an inputted signal, a signal input unit connected to said latching unit and a clock control unit connected to said signal input unit, wherein said clock control unit comprises a first switch element, a second switch element connected to said first switch element and an inverter connected to said second switch element, and a clock signal input end is connected to both said first switch element and said inverter,
- wherein said first switch element comprises a first FET, said second switch element comprises a second FET,
- wherein a gate electrode of said first FET and an input end of said inverter are both connected to said clock signal input end, a source electrode of said first FET and a ground terminal are connected, a drain electrode of said first FET and a source electrode of said second FET are connected, a gate electrode of said second FET and an output end of said inverter are connected, and a drain electrode of said second FET is connected to said signal input unit.
Dependencies are inferred from the claim text.