Reduced area schmitt trigger circuit
AssigneeSTMicroelectronics International N.V.
InventorRajeev Jain
Life of this patent
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Abstract
A Schmitt trigger circuit includes a first inverter having an input coupled to an input terminal; a second inverter having an input coupled to the input terminal; a first transistor having a source coupled to VDD, a drain coupled to an output of the first inverter, and a gate coupled to an output terminal; a second transistor having a source coupled to ground, a drain coupled to an output of the second inverter, and a gate coupled to the output terminal; a third transistor having a source coupled to VDD, a drain coupled to the output terminal, and a gate coupled to the output of the first inverter; and a fourth transistor having a source coupled to ground, a drain coupled to the output terminal, and a gate coupled to the output of the second inverter.
Claims15
A Schmitt trigger circuit comprising:
- an input terminal;
- an output terminal;
- a first inverter having an input coupled to the input terminal;
- a second inverter having an input coupled to the input terminal;
- a first transistor directly coupled between VDD and the output of the first inverter, and a gate directly coupled to the output terminal;
- a second transistor directly coupled between the output of the second inverter and ground, and a gate directly coupled to the output terminal;
- a third transistor having a gate coupled to the output of the first inverter;
- and
- a fourth transistor having a gate coupled to the output of the second inverter,
- wherein a current path of the third and fourth transistors are coupled together to form the output terminal.
A Schmitt trigger circuit comprising:
- a first inverter having an input coupled to an input terminal;
- a second inverter having an input coupled to the input terminal;
- a first transistor having a source coupled to VDD, a drain directly coupled to an output of the first inverter, and a gate directly coupled to an output terminal;
- a second transistor having a source directly coupled to ground, a drain directly coupled to an output of the second inverter, and a gate coupled to the output terminal;
- a third transistor having a source coupled to VDD, a drain directly coupled to the output terminal, and a gate coupled to the output of the first inverter;
- and
- a fourth transistor having a source coupled to ground, a drain coupled to the output terminal, and a gate coupled to the output of the second inverter.
A Schmitt trigger circuit comprising:
- a first inverter having an input coupled to an input terminal;
- a second inverter having an input coupled to the input terminal;
- a first transistor having a source directly coupled to VDD, a drain directly coupled to an output of the first inverter, and a gate coupled to an output terminal;
- a second transistor having a source coupled to ground, a drain directly coupled to an output of the second inverter, and a gate directly coupled to the output terminal;
- a third transistor having a source coupled to VDD, a drain directly coupled to the output terminal, and a gate coupled to the output of the first inverter;
- and
- a fourth transistor having a source coupled to ground, a drain coupled to the output terminal, and a gate coupled to the output of the second inverter.
Dependencies are inferred from the claim text.