Delay lock loop with a charge pump, loop filter, and method of phase locking of a delay lock loop
AssigneeEtron Technology, Inc.
InventorKuang-Fu Teng
Life of this patent
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Abstract
A delay lock loop includes a phase frequency detector, a loop filter, and a voltage controlled delay circuit. The phase frequency detector is used for outputting an upper switch signal or a lower switch signal according to a reference clock and a feedback clock. The loop filter includes a first capacitor, a second capacitor, and a first switch. The first capacitor is charged or discharged and the first switch is turned off during a phase tracking period. The first capacitor and the second capacitor are charged or discharged and the first switch is turned on during a phase locking period. The voltage controlled delay circuit is used for outputting the feedback clock according to the reference clock and a control voltage outputted by the loop filter.
Claims12
A delay lock loop, comprising:
- a phase frequency detector having a first input terminal for receiving a reference clock, a second input terminal for receiving a feedback clock, a first output terminal for outputting an upper switch signal, and a second output terminal for outputting a lower switch signal;
- a loop filter having a first input terminal for receiving the upper switch signal, a second input terminal for receiving the lower switch signal, and an output terminal for outputting a control voltage, wherein the loop filter includes a first capacitor, a second capacitor, and a first switch, and the first switch is coupled between a first terminal of the first capacitor and a first terminal of the second capacitor, wherein the first capacitor is charged/discharged and the first switch is turned off when the loop filter is in phase tracking, and the first switch is turned on when the loop filter is in phase locking;
- and
- a voltage control delay line having a first input terminal for receiving the reference clock, a second terminal coupled to the output terminal of the loop filter for receiving the control voltage, and an output terminal for outputting the feedback clock.
A method of phase locking of a delay lock loop, the method comprising:
- a phase frequency detector outputting an upper switch signal or a lower switch signal according to a reference clock and a feedback clock;
- a loop filter charging/discharging a first capacitor according to the upper switch signal/the lower switch signal when the loop filter is in phase tracking, charging/discharging a second capacitor by a buffer, and outputting a control voltage;
- and
- a voltage control delay line synchronizing the feedback clock with the reference clock according to the control voltage and the reference clock, and outputting the feedback clock.
Dependencies are inferred from the claim text.