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US 8,476,943 B2Granted
Semiconductor device
AssigneeHynix Semiconductor Inc.
InventorJung-Hoon Park
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes: a clock input unit configured to receive a system clock and a data clock externally; a phase dividing unit configured to generate a plurality of multi-system clocks in response to the system clock, wherein each of the multi-system clocks has an individual phase difference; a phase detecting unit configured to detect phase differences between the plurality of multi-system clock and the data clock and to generating generate a training information signal in response to the detection result; and a signal transmitting unit configured to transmit the training information signal.
Claims21
A semiconductor device, comprising:
- a clock input unit configured to receive a system clock and a data clock externally;
- a phase dividing unit configured to generate a plurality of multi-system clocks in response to the system clock, wherein each of the multi-system clocks has an individual phase difference;
- a phase detecting unit configured to detect phase differences between one of the plurality of multi-system clocks and the data clock to generate a training information signal in response to the detection result;
- and
- a signal transmitting unit configured to transmit the training information signal,
- wherein the phase detecting unit includes:
- a plurality of phase comparing units configured to compare phases between each of the plurality of multi-system clocks and the data clock, respectively, to output a plurality of comparison signals;
- and
- a logic level changing unit configured change a logic level of the training information signal in response to the plurality of comparison signals,
- wherein the data clock and the plurality of multi-system clocks have the same frequency.
7 more elements
A semiconductor device, comprising:
- a clock input unit configured to receive a system clock and a data clock externally;
- a phase dividing unit configured to generate a plurality of multi-system clocks each having an individual phase difference based on the system clock;
- a clock dividing unit configured to generate a data dividing clock with the same frequency as the plurality of multi-system clocks by dividing a frequency of the data clock;
- a phase detecting unit configured to detect phase differences between the plurality of multi-system clocks and the data dividing clock to generate a training information signal in response to the detection result;
- and
- a signal transmitting unit configured to transmit the training information signal,
- wherein the phase detecting unit includes:
- a plurality of phase comparing units configured to compare phases between each of the plurality of multi-system clocks and the data dividing clock, respectively, to output a plurality of comparison signals;
- and
- a logic level changing unit configured to change a logic level of the training information signal in response to the plurality of comparison signals.
7 more elements
A semiconductor device, comprising:
- a clock input unit configured to receive a system clock and a data clock from outside;
- a first clock dividing unit configured to divide a frequency of the system clock by a first ratio to output a system dividing clock;
- a phase dividing unit configured to generate a plurality of multi-system dividing clocks having a phase difference of a dedicated size respectively in response to the system dividing clock;
- a second clock dividing unit configured to divide a frequency of the data clock by a second ratio to generate a data dividing clock;
- a phase detecting unit configured to detect phase differences between the plurality of multi-system dividing clocks and the data dividing clock respectively to generate a training information signal in response to the detection result;
- and
- a signal transmitting unit configured to transmit the training information signal,
- wherein the phase detecting unit includes:
- a plurality of phase comparing units configured to compare phases between the plurality of multi-system dividing clocks and the data dividing clock, respectively, to output a plurality of comparison signals;
- and
- a logic level changing unit configured to change a logic level of the training information signal in response to the comparison signals output from the phase comparing units,
- wherein the data dividing clock and the plurality of multi-system dividing clocks have the same frequency.
9 more elements
Dependencies are inferred from the claim text.