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US 8,476,941 B2Granted
Buffer circuit for a capacitive load of high value
AssigneeSTMicroelectronics S.r.l.
InventorFrançois Agut
Life of this patent
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Abstract
A buffer circuit including an input terminal capable of receiving an input signal and an output terminal capable of being connected to a capacitive load, including an output circuit a series connection, between two terminals of application of a power supply voltage, of a first MOS transistor, a first and a second resistor of adjustable values, and a second MOS transistor, and means for controlling said first and second transistors receiving the input signal The buffer circuit further includes means for comparing the voltage on the output terminal of the circuit with at least one threshold voltage, the comparison means being connected to said control means.
Claims20
A buffer circuit comprising:
- an output circuit comprising a series connection, between two terminals of application of a power supply voltage, of a first MOS transistor, a first and a second resistor of adjustable values, and a second MOS transistor,
- control means for controlling said first and second MOS transistors, and receiving an input signal, and
- comparison means for comparing the voltage on an output terminal of the buffer circuit with a threshold voltage, the comparison means being connected to said control means, the comparison means comprising a first and a second comparator, each receiving, on a first one of its input terminals, a signal from the output terminal and, on a second one of its input terminals, respectively, a first and a second threshold voltage, the first and second threshold voltages being equal.
A system comprising:
- a signal generating circuit having a first output node;
- an output buffer having a first input node coupled to said first output node, and a second output node, said output buffer including:
- a control circuit having a second input node coupled to the first input node, a third input node coupled to a comparison circuit, and a third output node coupled to an output circuit;
- said comparison circuit, having a fourth input node coupled to said second output node, a fifth input node coupled to a first reference voltage, and a sixth input node coupled to a second reference voltage;
- and
- said output circuit having a seventh input node coupled to said third output of said control circuit and having a fourth output node coupled to said fourth input node of said comparison circuit, and having a series connection, between two terminals of application of a power supply voltage, a first MOS transistor, a first and a second resistor of adjustable values, and a second MOS transistor, the first and second resistors of adjustable values respectively including a plurality of parallel branches, each branch having a first terminal at a power supply node and a second terminal at the second output node and each branch including a resistive element and a transistor element in series.
3 more elements
A method of buffering a signal comprising:
- receiving a signal;
- in response to receiving the signal, coupling an output node to a first voltage node, when the signal is of a first logical state;
- comparing a voltage level on the output node to a first and a second threshold voltage, the first and second threshold voltages being equal;
- decoupling the output node from the first voltage node when the voltage level on the output node exceeds the first threshold voltage;
- and
- maintaining the voltage level on the output node until the signal changes logical state;
- in response to receiving the signal, coupling the output node to a second voltage node, when the signal is of a second logical state;
- comparing a voltage level on the output node to the first and the second threshold voltage;
- and
- decoupling the output node from the second voltage node when the voltage level on the output node falls below the second threshold voltage.
7 more elements
A buffer circuit comprising:
- an output circuit comprising a series connection, between two terminals of application of a power supply voltage, of a first MOS transistor, a first and a second resistor of adjustable values, and a second MOS transistor, wherein the first and second resistors of adjustable values respectively include a plurality of parallel branches, each branch having a first terminal at a power supply node and a second terminal at an output terminal of the buffer circuit and each branch including a resistive element and a transistor element in series,
- control means for controlling said first and second MOS transistors, and receiving an input signal, and
- comparison means for comparing the voltage on the output terminal of the buffer circuit with a threshold voltage, the comparison means being connected to said control means.
A system comprising:
- a signal generating circuit having a first output node;
- an output buffer having a first input node coupled to said first output node, and a second output node, said output buffer including:
- a control circuit having a second input node coupled to the first input node, a third input node coupled to a comparison circuit, and a third output node coupled to an output circuit;
- said comparison circuit, having a fourth input node coupled to said second output node, a fifth input node coupled to a first reference voltage, and a sixth input node coupled to a second reference voltage, the first reference voltage being equal to the second reference voltage;
- and
- said output circuit having a seventh input node coupled to said third output of said control circuit and having a fourth output node coupled to said fourth input node of said comparison circuit.
3 more elements
Dependencies are inferred from the claim text.