Device and method for generating three mode signal

A device for generating three mode signals, the device comprising:

• a first resistor including a first terminal and a second terminal, the first terminal of the first resistor being connected to an input terminal to receive three input signals of driving voltage, open, and ground;
• a first metal oxide semiconductor (MOS) transistor including a gate for receiving a first MOS reference voltage, a drain for receiving a power voltage, and a source, the first MOS transistor having a breakdown predetermined voltage;
• a second resistor including a first terminal and a second terminal, the first terminal of the second resistor being connected to the source of the first MOS transistor;
• a third resistor including a first terminal and a second terminal, the first terminal of the third resistor being grounded;
• a first node connected to the second terminals of the first resistor, the second resistor, and the third resistor;
• a first amplifier including a non-inverting input terminal, an inverting input terminal, and an output terminal, the non-inverting input terminal being connected to the first node;
• a second node connected to the inverting input terminal of the first amplifier;
• a second MOS transistor including a drain for receiving a power voltage, a gate connected to the output terminals of the first amplifier, and a source connected to the second node;
• a fourth resistor including a first terminal and a second terminal, the first terminal of the fourth resistor being connected to the second node;
• a third node connected to the second terminal of the fourth resistor;
• a fifth resistor including a first terminal and a second terminal, the first terminal of the fifth resistor being connected to the third node and the second terminal of the fifth resistor being grounded;
• a second amplifier including a non-inverting input terminal connected to the third node, an inverting input terminal for receiving a first reference voltage, and an output terminal, the second amplifier configured to output a first signal;
• and
• a third amplifier including a non-inverting input terminal connected to the second node, an inverting input terminal for receiving a second reference voltage, and an output terminal, the third amplifier configured to output a second signal, wherein
• a following condition is satisfied
• VDD×R3/(R1+R3)>2Vr1,
• Vr1<(VM1−Vth )×R3/(R2+R3)<2Vr1, and
• (VM1−Vth)×(R1//R3)/(R2+(R1//R3))<Vr1, where R=R5 and Vr1=Vr2 and R1 is resistance of the first resistor, R2 is resistance of the second resistor, R3 is resistance of the third resistor, VDD is the driving voltage, Vr1 is the first reference voltage, Vr2 is the second reference voltage, VM1 is the first MOS reference voltage, and Vth is the breakdown voltage.

A device for generating three mode signals, the device comprising:

• a voltage setting block including
• one input terminal configured to receive three input signals of high voltage, open, and low voltage,
• a first resistor including a first terminal and a second terminal, the first terminal of the first resistor being connected to the input terminal,
• a first metal oxide semiconductor (MOS) transistor including a gate for receiving a first MOS reference voltage, a drain for receiving a power voltage, and a source, the first MOS transistor having a predetermined breakdown voltage,
• a second resistor including a first terminal and a second terminal, the first terminal of the second resistor being connected to the source of the first MOS transistor,
• a third resistor including a first terminal and a second terminal, the first terminal of the third resistor being grounded, and
• a first node connected to the second terminals of the first resistor, the second resistor, and the third resistor, wherein the voltage setting block is configured to set three voltages based on the three input signals;
• and
• an output block including two output terminals and a second node configured to receive the three voltages from the voltage setting block, and configured to output three combined signals of high-high, low-high, and low-low voltages by comparing each of the three voltages received through the second node with a reference voltage.