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US 8,476,932 B2Granted
Multiplex gate driving circuit
AssigneeAu Optronics Corporation
InventorsHsiao-Wen Wang, Yu-Hsuan Li, Jui-Chi Lo, Chun-Hung Kuo, Sheng-Chao Liu
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Abstract
A multiplex gate driving circuit includes plural driving modules. In comparison with the prior art, each driving stage of the driving module has less number of transistors. From the first to the seventh example, each driving stage is implemented by only four transistors. In the eighth example and the ninth example, each driving stage is implemented by only two transistors. In other words, the driving stage of the multiplex gate driving circuit has less number of transistors, thereby reducing the layout area of the invisible zone of the LCD panel.
Claims25
A multiplex gate driving circuit, comprising:
- m shift registers for receiving a clock signal and sequentially generating m master signals;
- and
- n driving stages for respectively receiving n slave signals and sequentially generating n gate driving signals, wherein a duty cycle of each slave signal is equal to 1/n;
- wherein the m master signals are non-overlapped positive pulses with a first width, and an x-th shift register of the m shift registers generates an x-th master signal, a phase difference between every two adjacent slave signals is equal to 360/n degrees, and each of the n slave signals includes plural positive pulses;
- wherein an i-th driving stage of the n driving stages comprises an n-type transistor and a p-type transistor, the n-type transistor has a control terminal receiving an i-th slave signal of the n slave signals, a first terminal receiving the x-th master signal and a second terminal generating an i-th gate driving signal of the n gate driving signals, the p-type transistor has a control terminal receiving the i-th slave signal, a first terminal connected with the second terminal of the n-type transistor and a second terminal receiving an inverted power-off control signal.
2 more elements
A multiplex gate driving circuit, comprising
- m shift registers for receiving a clock signal and sequentially generating m master signals;
- and
- n driving stages for respectively receiving n slave signals and sequentially generating n gate driving signals, wherein a duty cycle of each slave signal is equal to 1/n;
- wherein the m master signals are non-overlapped positive pulses with a first width, and an x-th shift register of the m shift registers generates an x-th master signal, a phase difference between every two adjacent slave signals is equal to 360/n degrees, and each of the n slave signals includes plural negative pulses;
- wherein an i-th driving stage of the n driving stages comprises an n-type transistor and a p-type transistor, the p-type transistor has a control terminal receiving an i-th slave signal of the n slave signals, a first terminal receiving the x-th master signal and a second terminal generating an i-th gate driving signal of the n gate driving signals, and the n-type transistor has a control terminal receiving the i-th slave signal, a first terminal connected with the second terminal of the p-type transistor and a second terminal receiving an inverted power-off control signal.
2 more elements
A multiplex gate driving circuit, comprising:
- m shift registers for receiving a clock signal and sequentially generating m master signals;
- and
- n driving stages for respectively receiving n slave signals and sequentially generating n gate driving signals, wherein a duty cycle of each slave signal is equal to 1/n;
- wherein the m master signals are non-overlapped negative pulses with a first width, and an x-th shift register of the m shift registers generates an x-th master signal, a phase difference between every two adjacent slave signals is equal to 360/n degrees, and each of the n slave signals includes plural positive pulses;
- wherein an i-th driving stage of the n driving stages comprises an n-type transistor, a p-type transistor and an inverter, the n-type transistor has a control terminal receiving an i-th slave signal of the n slave signals and a first terminal receiving the x-th master signal, the inverter has an input terminal connected with a second terminal of the n-type transistor and an output terminal generating an i-th gate driving signal of the n gate driving signals, and the p-type transistor has a control terminal receiving the i-th slave signal, a first terminal connected with the second terminal of the n-type transistor and a second terminal receiving a power-off control signal.
2 more elements
A multiplex gate driving circuit, comprising:
- m shift registers for receiving a clock signal and sequentially generating m master signals;
- and
- n driving stages for respectively receiving n slave signals and sequentially generating n gate driving signals, wherein a duty cycle of each slave signal is equal to 1/n;
- wherein the m master signals are non-overlapped negative pulses with a first width, and an x-th shift register of the m shift registers generates an x-th master signal, a phase difference between every two adjacent slave signals is equal to 360/n degrees, and each of the n slave signals includes plural negative pulses.
1 more element
Dependencies are inferred from the claim text.