Level shifter with embedded logic and low minimum voltage

A memory circuit comprising:

• a memory array;
• a word line driver circuit coupled to the memory array and configured to generate a word line for the memory array, wherein the word line driver includes a precharge input signal;
• and
• a level shifter configured to generate the precharge input signal to the word line driver circuit, the level shifter including:
• shifting circuitry comprising a first leg including a first transistor controlled by a first input signal to the level shifter and a second transistor controlled by the first input signal, the first input signal from a source voltage domain and the level shifter configured to shift the first input signal to a target voltage domain, and the shifting circuitry comprising a second leg including a third transistor controlled by a complement of the first input signal and a fourth transistor controlled by a complement of the first input signal;
• a first input transistor controlled responsive to a second input signal, wherein the first input transistor includes a drain coupled to a first node between the first transistor and the second transistor;
• and
• a second input transistor controlled responsive to the second input signal, wherein the second input transistor includes a drain coupled to a second node between the third transistor and the fourth transistor, wherein the first input transistor is a same type of transistor as the second input transistor, and wherein, responsive to an assertion of the second input signal, the first input transistor and the second input transistor are configured to establish a same voltage on the first node and the second node.

An integrated circuit comprising:

• a logic circuit operable in a source voltage domain;
• and
• a memory circuit coupled to the logic circuit and operable in a target voltage domain, wherein the memory circuit comprises a level shifter including:
• shifting circuitry comprising a first leg including a first transistor controlled by a first input signal to the level shifter and a second transistor controlled by the first input signal, the first input signal from the source voltage domain and the level shifter configured to shift the first input signal to the target voltage domain, and the shifting circuitry comprising a second leg including a third transistor controlled by a complement of the first input signal and a fourth transistor controlled by a complement of the first input signal;
• a first input transistor controlled responsive to a second input signal, wherein the first input transistor includes a drain coupled to a first node between the first transistor and the second transistor;
• and
• a second input transistor controlled responsive to the second input signal, wherein the second input transistor includes a drain coupled to a second node between the third transistor and the fourth transistor, wherein the first input transistor is a same type of transistor as the second input transistor, and wherein, responsive to an assertion of the second input signal, the first input transistor and the second input transistor are configured to establish a same voltage on the first node and the second node.