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US 8,476,929 B2Granted
Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHajime Kimura
Life of this patent
Estimating the term…
Abstract
In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly.
Claims24
A semiconductor device comprising:
- a first inverter;
- a circuit comprising:
- a second inverter including an output electrically connected to an output of the first inverter, and comprising a first transistor of one of a n-channel type and a p-channel type, and a second transistor of another channel type than the first transistor, a terminal of the first transistor and a terminal of the second transistor forming the output of the second inverter;
- and
- a third transistor electrically connected in series with the first transistor and the second transistor between a first potential power supply line and a second potential power supply line, without other intervening component between the lines, so that, when the circuit is in operation, the second inverter is constantly supplied with a power supply potential supplied through one of the first potential power supply line and the second potential power supply line;
- and
- a third inverter including an input electrically connected to an output of the first inverter and to an output of the second inverter, and an output electrically connected to an input of the second inverter.
4 more elements
A semiconductor device comprising:
- a first circuit comprising:
- a first wiring;
- a first input terminal;
- a second input terminal;
- a first output terminal;
- a second wiring;
- a first n-channel transistor including a gate electrically connected to the first input terminal, and a first terminal electrically connected to the first wiring;
- a second n-channel transistor including a gate electrically connected to the second input terminal, a first terminal electrically connected a second terminal of the first n-channel transistor, and a second terminal electrically connected to the first output terminal;
- and
- a first p-channel transistor including a gate electrically connected to the second input terminal and to the gate of the second n-channel transistor, a first terminal electrically connected to the second terminal of the second n-channel transistor and to the first output terminal, and a second terminal electrically connected to the second wiring so that, when the first circuit is in operation, the first p-channel transistor is constantly supplied with a high power source potential through the second wiring;
- a second circuit comprising:
- a third input terminal;
- a fourth input terminal;
- a third wiring;
- a fourth wiring;
- a third n-channel transistor including a gate electrically connected to the third input terminal, a first terminal electrically directly connected to the third wiring so that, when the second circuit is in operation, the third n-channel transistor is constantly supplied with a low power source potential through the third wiring, and a second terminal electrically connected to the first output terminal of the first circuit;
- a second p-channel transistor including a gate electrically connected to the third input terminal and to the gate of the third n-channel transistor, and a first terminal electrically connected to the second terminal of the third n-channel transistor and to the first output terminal of the first circuit;
- and
- a third p-channel transistor including a gate electrically connected to the fourth input terminal, a first terminal electrically connected to a second terminal of the third p-channel transistor, and a second terminal electrically connected to the fourth wiring;
- and
- a third circuit comprising:
- a fifth wiring;
- a sixth wiring;
- a fourth n-channel transistor including a gate electrically connected to the first output terminal of the first circuit, a first terminal electrically connected to the fifth wiring, and a second terminal electrically connected to the third input terminal of the second circuit;
- and
- a fourth p-channel transistor including a gate electrically connected to the first output terminal of the first circuit and to the gate of the fourth n-channel transistor, a first terminal electrically connected to the second terminal of the fourth n-channel transistor and to the third input terminal of the second circuit, and a second terminal electrically connected to the sixth wiring.
23 more elements
A semiconductor device comprising:
- a first circuit comprising:
- a first wiring;
- a first input terminal;
- a second input terminal;
- a first output terminal;
- a second wiring;
- a first p-channel transistor including a gate electrically connected to the first input terminal, and a first terminal electrically connected to the first wiring;
- a second p-channel transistor including a gate electrically connected to the second input terminal, a first terminal electrically connected a second terminal of the first p-channel transistor, and a second terminal electrically connected to the first output terminal;
- and
- a first n-channel transistor including a gate electrically connected to the second input terminal and to the gate of the second p-channel transistor, a first terminal electrically connected to the second terminal of the second p-channel transistor and to the first output terminal, and a second terminal electrically connected to the second wiring so that, when the first circuit is in operation, the first n-channel transistor is constantly supplied with a low power source potential through the second wiring;
- a second circuit comprising:
- a third input terminal;
- a fourth input terminal;
- a third wiring;
- a fourth wiring;
- a third p-channel transistor including a gate electrically connected to the third input terminal, a first terminal electrically directly connected to the third wiring so that, when the second circuit is in operation, the third p-channel transistor is constantly supplied with a high power source potential through the third wiring, and a second terminal electrically connected to the first output terminal of the first circuit;
- a second n-channel transistor including a gate electrically connected to the third input terminal and to the gate of the third p-channel transistor, and a first terminal electrically connected to the second terminal of the third p-channel transistor and to the first output terminal of the first circuit;
- and
- a third n-channel transistor including a gate electrically connected to the fourth input terminal, a first terminal electrically connected to a second terminal of the third n-channel transistor, and a second terminal electrically connected to the fourth wiring;
- and
- a third circuit comprising:
- a fifth wiring;
- a sixth wiring;
- a fourth p-channel transistor including a gate electrically connected to the first output terminal of the first circuit, a first terminal electrically connected to the fifth wiring, and a second terminal electrically connected to the third input terminal of the second circuit;
- and
- a fourth n-channel transistor including a gate electrically connected to the first output terminal of the first circuit and to the gate of the fourth p-channel transistor, a first terminal electrically connected to the second terminal of the fourth p-channel transistor and to the third input terminal of the second circuit, and a second terminal electrically connected to the sixth wiring.
23 more elements
Dependencies are inferred from the claim text.