US 8,476,926 B1 · Method and apparatus for implementing periphery devices on a programmable circuit using partial reconfiguration

Abstract

A programmable circuit includes a physical interface at an input output (IO) periphery of the programmable circuit. The programmable circuit also includes a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module.

Claims22

Dependent claims

A programmable circuit comprising:

a physical interface at an input output (IO) periphery of the programmable circuit;
and
a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module.

Dependencies are inferred from the claim text.

Facts

Application

13/368,437Filed 8 Feb 2012

Granted

2 Jul 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/343
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: logical level

Abstract

Facts

Application

13/368,437Filed 8 Feb 2012

Granted

2 Jul 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/343
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: logical level

Method and apparatus for implementing periphery devices on a programmable circuit using partial reconfiguration

Life of this patent

Abstract

Claims22

Method and apparatus for implementing periphery devices on a programmable circuit using partial reconfiguration

Life of this patent

Abstract

Claims22