Configuration of connections in a 3D stack of integrated circuits

A method for providing a connection configuration for a 3D chip stack having two or more strata, each of the two or more strata having multiple circuit components, a front-side and a back-side, the method comprising:

• providing a connection pair having as members a front-side connection and a backside connection unconnected to the front-side connection and co-located with respect to each other on a given stratum from the two or more strata;
• respectively connecting the front-side connection and the backside connection to different ones of the multiple circuit components on the given stratum;
• and
• connecting at least one of the front-side connection and the backside connection to a particular one of the multiple circuit components on an adjacent stratum to the given stratum from among the two or more strata.

A connection configuration for a 3D chip stack having two or more strata including a first terminal stratum on one end of the 3D chip stack and a second terminal stratum on an opposing end of the 3D chip stack, each of the two or more strata having multiple circuit components, a front-side and a back-side, the first terminal stratum having the front-side being externally accessible, the connection configuration comprising:

• an array of backside connections on the two or more strata;
• and
• an array of front-side connections on the two or more strata, each of the front-side connections being co-located in relation to a respective one of the backside connections on a respective same one of the two or more strata, each of the front-side connections, except last ones of the front-side connections on each of the two or more strata in a selected direction, being connected to a respective one of the backside connections that is adjacent to a co-located one of the backside connections on the respective same one of the two or more strata, each of the last ones of the front-side connections being respectively connected to a given one of the multiple circuit components on the respective same one of the two or more strata, and
• wherein each of the backside connections is connected to a co-located one of the front side connections on an adjacent one of the two or more strata, and each of the backside connections on the first terminal stratum are accessible to and from the at least some of the multiple circuit components on the first terminal stratum.

A method for providing a connection configuration for a multiple layer chip stack having two or more strata including a first terminal stratum on one end of the 3D chip stack and a second terminal stratum on an opposing end of the 3D chip stack, each of the two or more strata having multiple circuit components, a front-side and a back-side, the first terminal stratum having the front-side being externally accessible, the method comprising:

• providing an array of backside connections on the two or more strata;
• and
• providing an array of front-side connections on the two or more strata, each of the front-side connections being co-located in relation to a respective one of the backside connections on a respective same one of the two or more strata, each of the front-side connections, except last ones of the front-side connections on each of the two or more strata in a selected direction, being connected to a respective one of the backside connections that is adjacent to a co-located one of the backside connections on the respective same one of the two or more strata, each of the last ones of the front-side connections being respectively connected to a given one of the multiple circuit components on the respective same one of the two or more strata, and
• wherein each of the backside connections is connected to a co-located one of the front side connections on an adjacent one of the two or more strata, and each of the backside connections on the first terminal layer are accessible to and from the at least some of the multiple circuit components on the first terminal stratum.