Through-silicon vias and methods for forming the same

An integrated circuit structure comprising:

• a semiconductor substrate;
• a plurality of dielectric layers over the semiconductor substrate;
• a through-silicon via (TSV) penetrating the plurality of dielectric layers and the semiconductor substrate, wherein the TSV is formed of a conductive material and extends to a back surface of the semiconductor substrate;
• a TSV pad directly over the plurality of dielectric layers, wherein the TSV pad is adjacent the TSV and on a first side, and not on a second side, of the TSV, wherein the first and the second sides are opposite to each other relative to an axis of the TSV, and are on a same side of the semiconductor substrate, and wherein the axis is perpendicular to a major surface of the semiconductor substrate;
• and
• a metal line overlying and electrically connecting the TSV pad and the TSV.

A method of forming an integrated circuit structure, the method comprising:

• providing a wafer comprising:
• a semiconductor substrate;
• and
• a through-silicon via (TSV) pad over the semiconductor substrate;
• forming a TSV opening extending from a top surface of the wafer into the semiconductor substrate, wherein the TSV pad is adjacent the TSV opening, and wherein the TSV opening does not extend through the TSV pad;
• forming a TSV in the TSV opening;
• and
• forming a metal line electrically connecting the TSV and the TSV pad.

A method of forming an integrated circuit structure, the method comprising:

• providing a wafer comprising:
• a semiconductor substrate;
• and
• a through-silicon via (TSV) pad over the semiconductor substrate;
• forming a TSV opening extending into the semiconductor substrate and adjacent the TSV pad, wherein the TSV pad is on a first side, and not on a second side, of the TSV opening, wherein the first and the second sides are opposite to each other relative to an axis of the TSV opening, and are on a same side of the semiconductor substrate, and wherein the axis is perpendicular to a major surface of the semiconductor substrate;
• blanket forming a diffusion barrier layer over the wafer, wherein the diffusion barrier layer extends into the TSV opening;
• blanket forming a copper seed layer on the diffusion barrier layer;
• forming and patterning a mask layer, wherein the TSV pad, the TSV opening, and a region therebetween are exposed through the mask layer;
• selectively forming a copper layer on the copper seed layer, wherein the copper layer fills the TSV opening to form a TSV, and wherein the copper layer extends over the TSV pad;
• removing the mask layer to expose portions of the copper seed layer and the diffusion barrier layer underlying the mask layer;
• etching the exposed portions of the copper seed layer;
• and
• etching the exposed portions of the diffusion barrier layer.