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US 8,476,767 B2Granted
Stacked layer type semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorHo Cheol Lee
Life of this patent
Estimating the term…
Abstract
A stacked layer type semiconductor device includes N memories each including at least one main via and (N−1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1.
Claims10
A stacked layer type semiconductor device comprising:
- a printed circuit board (PCB) substrate receiving a first access signal, a second access signal, a first data signal, and a second data signal from an external source;
- a second memory mounted on the PCB, the second memory including a third through-silicon via (TSV) receiving the first access signal and the first data signal from the PCB, a fourth TSV receiving the second access signal and the second data signal from the PCB, and a second memory buffer directly connected to the third via and receiving the first access signal and the first data signal therethrough;
- and
- a first memory mounted on the second memory, the first memory including a second TSV directly connected to the third TSV , a first TSV directly connected to the fourth TSV, and a first memory buffer directly connected to the first TSV and receiving the second access signal and the second data signal therethrough,
- wherein the second memory buffer is not connected to the first TSV and does not receive the second access signal or the second data signal, and the first memory buffer is not connected to the third via and does not receive the first access signal or the first data signal.
2 more elements
Dependencies are inferred from the claim text.