Electroplated posts with reduced topography and stress

A method of forming electroplated posts with a plurality of sizes on an integrated circuit, comprising;

• providing a semiconductor substrate having a plurality of bond pads of different sizes;
• depositing a dielectric layer over said bond pads and said integrated circuit;
• etching said dielectric layer to form a first dielectric patterned structure having first openings for electroplating over said bond pads, said first dielectric patterned structure including planarizing dielectric structures over at least some of said bond pads, wherein larger bond pads have more planarizing dielectric structures defined than smaller bond pads;
• depositing a electroplating layer over said integrated circuit;
• forming second openings in said electroplating layer over said bond pads;
• electroplating a metal within said second openings and within said first openings to form said posts, wherein said planarizing dielectric structures are enclosed by said posts on at least three sides.