US 8,476,752 B2Granted

Package structure for DC-DC converter

AssigneeAlpha and Omega Semiconductor Incorporated

InventorsYueh-Se Ho, Yan Xun Xue, Jun Lu

Life of this patent

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Abstract

A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

Claims8

Dependent claims

A package structure for DC-DC converter, comprising:

a high-side MOSFET chip (21) and a low-side MOSFET chip (22) respectively having a bottom drain electrode, a top gate electrode and a top source electrode;
a lead frame having a first die pad (11) and a second die pad (12), the first die pad having a first portion and a second portion wherein said high-side MOSFET chip (21) being disposed on the first portion of the first die pad (11) with its bottom drain electrode electrically connected with the first die pad (11);
a controller (40) disposed on the second portion of the first die pad (11) and being electrically connected with the top gate electrode of the high-side MOSFET chip (21);
and
a conductive interposer (30) disposed on top of the second die pad (12) and at least a portion of the high-side MOSFET chip (21) and being electrically connected with the top source electrode (211) of the high-side MOSFET chip (21), wherein said interposer (30) does not cover the controller (40);
wherein the low-side MOSFET chip (22) being disposed on the interposer (30) with its top gate electrode electrically connected with the controller (40) and its bottom drain electrode electrically connected with the top source electrode (211) of the high-side MOSFET chip (21).

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/494,219Filed 12 Jun 2012 · continuation
Priority: 14 Sep 2010
Published: US 2012/0061813 A14 Oct 2012
Granted: 2 Jul 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10W 90/811
Package configurations: multiple chips on leadframes
H10W 70/421
Leadframes: shapes or dispositions
H10W 70/466
Additional interconnections in combination with leadframes: tape carriers or flat leads
H10W 70/481
Leadframes: for devices being provided for in groups H10D8/00 - H10D48/00

Family

Application12/881,372Parent of this continuation · filed 14 Sep 2010
US 2012/0248593 A1Pre-grant publication · published 4 Oct 2012
US 8,217,503 B2Parent of this continuation
US 2012/0061813 A1Published application
US 8,476,752 B2This patent

From the US filing history. Foreign family members aren’t listed.