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AssigneeSK hynix Inc.
InventorsKyu Won Lee, Cheol Ho Joh, Eun-Hye Do, Ji Eun Kim, Hee Min Shin
Estimating the term…
A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.
A stacked semiconductor package comprising:
A method for manufacturing a stacked semiconductor package, comprising the steps of:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
Manufacture or treatment: using batch processing
By a substrate and the encapsulations: the substrate having spherical bumps for external connection
Package configurations
About 4 years 11 months of term left · ends 26 Sep 2031 (estimated)
The present application claims priority to Korean patent application number 10-2010-42457 filed on May 6, 2010, which is incorporated herein by reference in its entirety.
The present invention relates to a stacked semiconductor package and a method for manufacturing the same.
In the semiconductor industry, packaging technologies for semiconductor integrated circuits have continuously are being developed to meet the demands toward miniaturization and mounting efficiency. For example, the demand for miniaturization is accelerating the development of technologies for a package having a size approaching to that of a chip, and the demand for mounting reliability is highlighting the importance of packaging technologies for improving the efficiency of mounting work and mechanical and electrical reliability after mounting. Also, as miniaturization and high performance are demanded in electric and electronic products, stacking technologies have been suggested in the art and are currently being developed into various styles.
FIG. 1 is a cross-sectional view illustrating a known POP type stacked semiconductor package.
FIG. 2 is a perspective view illustrating a stacked semiconductor package in accordance with an exemplary embodiment of the present invention.
FIG. 3 is a cross-sectional view taken along the line I-I′ of FIG. 2.
Hereafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.
It is to be understood herein that the drawings are not necessarily to scale and in some instances proportions may have been exaggerated in order to more clearly depict certain features of the invention.
FIG. 2 is a perspective view illustrating a stacked semiconductor package in accordance with an exemplary embodiment of the present invention, FIG. 3 is a cross-sectional view taken along the line I-I′ of FIG. 2, and FIG. 4 is a partially broken-away perspective view of the semiconductor package shown in FIG. 2.