Geiger-mode photodiode with integrated and JFET-effect-adjustable quenching resistor, photodiode array, and corresponding manufacturing method

An integrated circuit, comprising:

• a first electronic device, including:
• a first semiconductor region of a first conductivity type;
• a second semiconductor region of a second conductivity type disposed in the first semiconductor region, dividing the first semiconductor region into at least first and second portions, and defining a pathway having a first area between the first and second portions;
• a third semiconductor region of the second conductivity type disposed in one of the first and second portions of the first semiconductor region and spaced from the pathway;
• and
• a fourth semiconductor region of the second conductivity type having an anode region flanked by an annular guard region having an annulus with an area that is larger than the area of the pathway.

A pixel array, comprising:

• multiple pixel sensors, each sensor including:
• a first semiconductor region of a first conductivity type and having a thickness of approximately 15 micrometers;
• a second semiconductor region of a second conductivity type disposed in the first semiconductor region, dividing the first semiconductor region into at least first and second portions, and defining a pathway between the first and second portions;
• and
• a third semiconductor region of the second conductivity type disposed in one of the first and second portions of the first semiconductor region and spaced from the pathway.

A system, comprising:

• a pixel array, including:
• multiple pixel sensors, each sensor including:
• a first semiconductor region of a first conductivity type;
• a second semiconductor region of a second conductivity type disposed in the first semiconductor region, dividing the first semiconductor region into at least first and second portions, and defining a pathway between the first and second portions, the pathway comprising a first area bounded by the second semiconductor region;
• a third semiconductor region of the second conductivity type disposed in one of the first and second portions of the first semiconductor region and spaced from the pathway;
• and
• a fourth semiconductor region of the second conductivity type disposed over the first semiconductor region and having a second area that is larger than the first area;
• and
• an integrated circuit coupled to the pixel array.