System for protection against electrostatic discharges in an electrical circuit

A device for protection against electrostatic discharges in an electrical circuit, having at least one fin pinch resistor, comprising:

• an electrically insulating layer;
• a fin structure formed on the electrically insulating layer, the fin structure having a first connection region, a second connection region and a channel region formed between the first connection region and the second connection region, wherein the connection regions and the channel region are either all n-doped or all p-doped, wherein the channel region is doped down to the electrically insulating layer, and wherein, during a first operating state of the electrical circuit, the first connection region is electrically coupled to a high electrical potential and the second connection region is electrically coupled to a lower electrical potential in case that the connection regions are n-doped and the first connection region is electrically coupled to a low electrical potential and the second connection region is electrically coupled to a higher electrical potential in case that the connection regions are p-doped, said first operating state being a normal operating state of the electrical circuit;
• a gate region formed at least over a part of the surface of the channel region;
• a gate control circuit, which is electrically coupled to the gate region and which is configured to control an electrical potential applied to the gate region in such a way that the channel region is pinched off during the first operating state of the electrical circuit, and that the electrical potential at the gate region follows an electrical potential at the first connection region during a second operating state of the electrical circuit, said second operating state being characterized by the occurrence of an ESD event.

An ESD protection element, comprising:

• an electrically insulating layer;
• a fin disposed on the electrically insulating layer, the fin having a first connection region, a second connection region and a channel region between the first and second connection regions, wherein the first and second connection regions and the channel region are either all n-doped or all p-doped, and wherein the channel region is doped down to the electrically insulating layer;
• a gate region disposed over the channel region;
• a gate control circuit coupled to the gate region, the gate control circuit applying a first electrical potential to the gate region during a normal operating state, and applying a second electrical potential to the gate region during an ESD event, wherein the first electrical potential substantially depletes the channel region of free charge carriers, and wherein the second electrical potential reduces the charge carrier depletion in the channel region.

An electrical circuit, comprising:

• at least one circuit element to be protected against an ESD event;
• an ESD protection element connected in parallel to the at least one circuit element, the ESD protection element comprising:
• an electrically insulating layer;
• a fin disposed on the electrically insulating layer, the fin having a first connection region, a second connection region and a channel region between the first and second connection regions, wherein the first and second connection regions and the channel region are either all n-doped or all p-doped, and wherein the channel region is doped down to the electrically insulating layer;
• a gate region disposed over the channel region;
• a gate control circuit coupled to the gate region, the gate control circuit applying a first electrical potential to the gate region during a normal operating state of the electrical circuit, and applying a second electrical potential to the gate region during the ESD event, wherein the first electrical potential substantially depletes the channel region of free charge carriers, and wherein the second electrical potential reduces the charge carrier depletion in the channel region.