Semiconductor memory device having a circuit formed on a single crystal semiconductor layer with varied germanium concentration

#This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2011-004954, filed Jan. 13, 2011, the entire contents of which are incorporated herein by reference.

#Embodiments described herein relate generally to a semiconductor memory device and a method of manufacturing the same.

#As a technique of increasing the density of a memory without depending on lithography, structures such as a structure in which a one-time-programmable (OTP) element is sandwiched between multiple interconnection layers and a structure in which a plurality of NAND flash memory layers are formed by repeating epitaxial growth of silicon films have been proposed. However, these structures have the problem that the number of times of lithography increases as the number of stacked layers increases. Therefore, a collectively processed, three-dimensionally stacked memory has been proposed as a technique replacing these structures.

#FIG. 1 is a sectional view showing a semiconductor memory device according to the first embodiment along the row and column directions;

#FIG. 2 is a perspective view of a memory cell string shown in FIG. 1;

#FIG. 3 is an enlarged sectional view of the memory cell string shown in FIG. 2;

#In general, according to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes a plurality of memory cells for storing data. The single-crystal semiconductor layer is formed on an insulating layer on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the insulating layer and memory cell array portion. The circuit portion is formed on the single-crystal semiconductor layer. The Ge concentration in the lower portion of the single-crystal semiconductor layer on the memory cell array portion is higher than that in the upper portion of the single-crystal semiconductor layer.

#<First Embodiment>

#A semiconductor memory device according to the first embodiment will be explained below with reference to FIGS. 1, 2, 3, 4, 5, 6, and 7. The first embodiment is an example in which a single-crystal semiconductor layer in which a control circuit is to be formed is formed immediately above a memory cell array.