US 8,476,706 B1Granted

CMOS having a SiC/SiGe alloy stack

AssigneeInternational Business Machines Corporation

InventorsDureseti Chidambarrao, Brian J. Greene, Yue Liang, Xiaojun Yu

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Abstract

A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.

Claims12

Dependent claims

A semiconductor structure comprising a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) located on a substrate,

wherein said PFET comprises a first silicon portion and a layer stack of a first silicon carbon alloy layer and a silicon germanium alloy layer, a combination of said first silicon portion and said layer stack includes a first source region, a first drain region, and a first body region, and said layer stack is in contact with a first gate dielectric that is in contact with a first gate electrode,
and wherein said NFET comprises a second silicon portion and a second silicon carbon alloy layer, a combination of said second silicon portion and said second silicon carbon alloy layer includes a second source region, a second drain region, and a second body region, and said second silicon carbon alloy layer is in contact with a second gate dielectric that is in contact with a second gate electrode,
and wherein said first gate dielectric and said second gate dielectric have a same composition and a same thickness.

Dependencies are inferred from the claim text.

Facts

Application: 13/343,472Filed 4 Jan 2012
Published: US 2013/0168695 A14 Jul 2013
Granted: 2 Jul 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/0278
Of lateral single-gate IGFETs: forming single crystalline channels on wafers after forming insulating device isolations
H10D 30/751
Insulated-gate field-effect transistors [IGFET]: having composition variations in the channel regions
H10D 84/0165
The components including insulated gates, e.g. IGFETs: the components including complementary IGFETs, e.g. CMOS devices