High voltage semiconductor device
AssigneeMacronix International Co., Ltd.
InventorsHsuehi Huang, Yin-Fu Huang, Shih-Chin Lien
Life of this patent
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Abstract
A semiconductor device for a high voltage application includes a doped source base region, an N+ source region, a P+ source region and a gate structure. The doped source base region has P-type. The N+ source region extends downwards into the doped source base region. The P+ source region is close to the N+ source region, extends downwards into the doped source base region, and is doped heavier than the doped source base region. The gate structure is coupled to the N+ source region and is near to the P+ source region.
Claims19
A semiconductor device, comprising:
- a doped source base region having P-type;
- an N+ source region extending downwards into the doped source base region;
- a P+ source region being close to the N+ source region, extending downwards into the doped source base region, and doped heavier than the doped source base region;
- and
- a gate structure coupled to the N+ source region, and being near to the P+ source region, wherein:
- the N+ source region comprises a plurality of source sub-regions;
- the P+ source region comprises a base sub-region and a plurality of salient sub-regions aligned laterally from the base sub-region;
- and
- each of the plurality of source sub-regions is disposed between two of the plurality of salient sub-regions.
A semiconductor device, comprising:
- a doped source base region having P-type;
- an N+ source region disposed in the doped source base region;
- a P+ source region being close to the N+ source region, disposed in the doped source base region, and doped heavier than the doped source base region;
- and
- a gate structure being near to the P+ source region, wherein:
- the N+ source region comprises a plurality of source sub-regions;
- the P+ source region comprises a base sub-region and a plurality of salient sub-regions aligned laterally from the base sub-region;
- and
- each of the plurality of source sub-regions is disposed between two of the plurality of salient sub-regions.
A semiconductor device, comprising:
- a doped source base region having N-type;
- a P+ source region disposed in the doped source base region;
- an N+ source region being close to the P+ source region, disposed in the doped source base region, and doped heavier than the doped source base region;
- and
- a gate structure being near to the N+ source region, wherein:
- the P+ source region comprises a plurality of source sub-regions;
- the N+ source region comprises a base sub-region and a plurality of salient sub-regions aligned laterally from the base sub-region;
- and
- each of the plurality of source sub-regions is disposed between two of the plurality of salient sub-regions.
Dependencies are inferred from the claim text.