Self aligned narrow storage elements for advanced memory device
AssigneeSpansion LLC
InventorSuketu Arun Parikh
Life of this patent
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Abstract
A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.
Claims20
A memory cell comprising:
- a first bitline element and a second bitline element co-located on a semiconductor substrate surface;
- a first sub-lithographic charge storage element and a second sub-lithographic charge storage element located between the first bitline element and the second bitline element, and a dielectric layer located between the first sub-lithographic charge storage element and the second sub-lithographic charge storage element;
- a first implanted portion of the semiconductor substrate located under the first sub-lithographic charge storage element and a second implanted portion of the semiconductor substrate located under the second sub-lithographic charge storage element;
- and
- a top gate over the first sub-lithographic charge storage element, the second sub-lithographic charge storage element and dielectric layer.
A memory cell comprising:
- two bitline elements on a semiconductor substrate;
- two sub-lithographic charge storage elements between the two bitline elements on the semiconductor substrate;
- a dielectric layer between the two sub-lithographic charge storage elements on the semiconductor substrate;
- implanted portions of the semiconductor substrate under the two sub-lithographic charge storage elements;
- and
- a top gate over the two sub-lithographic charge storage elements and dielectric layer.
A semiconductor structure comprising two or more memory cells, the memory cell comprising:
- two bitline elements on a semiconductor substrate;
- two sub-lithographic charge storage elements between the two bitline elements on the semiconductor substrate;
- a dielectric layer between the two sub-lithographic charge storage elements on the semiconductor substrate;
- implanted portions of the semiconductor substrate under the two sub-lithographic charge storage elements;
- and
- a top gate over the two sub-lithographic charge storage elements and dielectric layer.
Dependencies are inferred from the claim text.