Memory cell, memory device and method for manufacturing memory cell
AssigneeMacronix International Co., Ltd.
InventorsPo-Chou Chen, Yao-Wen Chang, I-Chen Yang
Life of this patent
Estimating the term…
Abstract
A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region.
Claims14
A memory cell, comprising:
- a substrate, having a first doped region, a second doped region and a channel region located between the first doped region and the second doped region;
- a stacked gate structure, disposed on the channel region, and at least comprising a charge trapping layer and a gate from bottom to top;
- and
- a first isolation structure, disposed in the substrate, connected to the first doped region and extending downwards from the first doped region for a predetermined length, wherein a bottom of the first isolation structure is lower than a bottom of the first doped region, and a width of the first isolation structure is smaller than a width of a space between the stacked gate structure and an adjacent gate structure.
A memory device, comprising:
- a driving circuit;
- and
- a memory cell array, coupled to the driving circuit, wherein the memory cell array has a plurality of memory cells connected with each other, and each of the memory cells comprises:
- a substrate, having a first doped region, a second doped region and a channel region located between the first doped region and the second doped region;
- a stacked gate structure, disposed on the channel region, and at least comprising a charge trapping layer and a gate from bottom to top;
- and
- a first isolation structure, disposed in the substrate, connected to the first doped region and extending downwards from the first doped region for a predetermined length, wherein a bottom of the first isolation structure is lower than a bottom of the first doped region, and a width of the first isolation structure is smaller than a width of a space between the stacked gate structure and an adjacent gate structure.
Dependencies are inferred from the claim text.