Thin film transistor with offset structure and electrodes in a symmetrical arrangement

A thin film transistor (TFT) comprising an active region divided into a first active region, a second active region, and a third active region, the active region comprising:

• a gate electrode;
• an active layer comprising a first active layer corresponding to the first active region, a second active layer corresponding to the second active region, and a third active layer corresponding to the third active region, the first active layer, the second active layer, and the third active layer overlapping with the gate electrode;
• a gate insulating layer between the gate electrode and the active layer;
• and
• a source/drain electrode layer comprising a first source/drain electrode and a second source/drain electrode that are electrically connected to the first active layer, a third source/drain electrode and a fourth source/drain electrode that are electrically connected to the second active layer, and a fifth source/drain electrode and a sixth source/drain electrode that are electrically connected to the third active layer,
• wherein:
• two source/drain electrodes selected from among the first to fourth source/drain electrodes overlap partially with the gate electrode,
• other two source/drain electrodes from among the first to fourth source/drain electrodes are offset from the gate electrode, and
• the first to sixth source/drain electrodes and the gate electrode are in a symmetrical arrangement.

A thin film transistor (TFT) comprising an active region divided into a first active region, a second active region, a third active region, and a fourth active region, the active region comprising:

• a gate electrode;
• an active layer comprising a first active layer corresponding to the first active region, a second active layer corresponding to the second active region, a third active layer corresponding to the third active region, and a fourth active layer corresponding to the fourth active region, the first active layer, the second active layer, the third active layer, and the fourth active layer overlapping with the gate electrode;
• a gate insulating layer between the gate electrode and the active layer;
• and
• a source/drain electrode layer comprising a first source/drain electrode and a second source/drain electrode that are electrically connected to the first active layer, a third source/drain electrode and a fourth source/drain electrode that are electrically connected to the second active layer, a fifth source/drain electrode and a sixth source/drain electrode that are electrically connected to the third active layer, and a seventh source/drain electrode and an eighth source/drain electrode that are electrically connected to the fourth active layer,
• wherein:
• two source/drain electrodes selected from among the third to sixth source/drain electrodes overlap partially with the gate electrode,
• other two source/drain electrodes from among the third to sixth source/drain electrodes are offset from the gate electrode, and
• the first to eighth source/drain electrodes and the gate electrode are in a symmetrical arrangement.

A thin film transistor (TFT) comprising an active region comprising:

• a gate electrode comprising a first gate electrode and a second gate electrode that are parallel with each other;
• an active layer overlapping with the first gate electrode and the second gate electrode, and comprising a first gate region corresponding to the first gate electrode, a second gate region corresponding to the second gate electrode, and an offset region extending from the first gate region to the second gate region;
• a gate insulating layer between the gate electrode and the active layer;
• and
• a source/drain electrode layer comprising a first source/drain electrode and a second source/drain electrode that are electrically connected to the active layer,
• wherein:
• the first source/drain electrode overlaps partially with the first gate electrode,
• the second source/drain electrode overlaps partially with the second gate electrode,
• the offset region does not overlap with any of the first gate electrode, the second gate electrode, the first source/drain electrode, and the second source/drain electrode, and
• the first and second source/drain electrodes and the gate electrode are in a symmetrical arrangement.