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US 8,476,626 B2Granted
Semiconductor memory device including semiconductor and oxide semiconductor transistors
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei Yamazaki, Jun Koyama, Kiyoshi Kato
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Abstract
It is an object to provide a semiconductor device with a novel structure. The semiconductor device includes memory cells connected to each other in series and a capacitor. One of the memory cells includes a first transistor connected to a bit line and a source line, a second transistor connected to a signal line and a word line, and a capacitor connected to the word line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor are connected to one another.
Claims32
A semiconductor device comprising:
- a source line;
- a bit line;
- a signal line;
- and
- a word line,
- wherein a plurality of memory cells are connected in series between the source line and the bit line,
- wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,
- wherein the first transistor is provided in a substrate containing a semiconductor material,
- wherein the second transistor comprises an oxide semiconductor layer,
- wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,
- wherein the source line and the first source electrode are electrically connected to each other,
- wherein the bit line and the first drain electrode are electrically connected to each other,
- wherein the signal line and the second gate electrode are electrically connected to each other, and
- wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another.
11 more elements
A semiconductor device comprising:
- a source line;
- a bit line;
- a signal line;
- a word line;
- a first selection line;
- a second selection line;
- a third transistor comprising a third gate electrode, the third gate electrode electrically connected to the first selection line;
- and
- a fourth transistor comprising a fourth gate electrode, the fourth gate electrode electrically connected to the second selection line,
- wherein a plurality of memory cells are connected in series between the source line and the bit line,
- wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,
- wherein the first transistor is provided in a substrate containing a semiconductor material,
- wherein the second transistor comprises an oxide semiconductor layer;
- wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,
- wherein the source line and the first source electrode are electrically connected to each other,
- wherein the bit line and the first drain electrode are electrically connected to each other,
- wherein the bit line is electrically connected to the first drain electrode through the third transistor,
- wherein the source line is electrically connected to the first source electrode through the fourth transistor,
- wherein the signal line and the second gate electrode are electrically connected to each other;
- and
- wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another.
18 more elements
A semiconductor device comprising:
- a source line;
- a bit line;
- a signal line;
- and
- a word line,
- wherein a plurality of memory cells are connected in series between the source line and the bit line;
- wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,
- wherein the first transistor is provided in a substrate containing a semiconductor material,
- wherein the second transistor comprises an oxide semiconductor layer,
- wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,
- wherein the source line and the first source electrode are electrically connected to each other,
- wherein the bit line and the first drain electrode are electrically connected to each other,
- wherein the first transistor comprises a channel formation region provided in the substrate containing the semiconductor material, impurity regions provided so as to interpose the channel formation region, a first gate insulating layer over the channel formation region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode which are electrically connected to the impurity regions,
- wherein the signal line and the second gate electrode are electrically connected to each other;
- and
- wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another.
13 more elements
A semiconductor device comprising:
- a source line;
- a bit line;
- a signal line;
- a word line;
- a first selection line;
- a second selection line;
- a third transistor comprising a third gate electrode, the third gate electrode electrically connected to the first selection line;
- and
- a fourth transistor comprising a fourth gate electrode, the fourth gate electrode electrically connected to the second selection line,
- wherein a plurality of memory cells are connected in series between the source line and the bit line,
- wherein one of the plurality of memory cells comprises a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor,
- wherein the first transistor is provided in a substrate containing a semiconductor material,
- wherein the second transistor comprises an oxide semiconductor layer,
- wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another,
- wherein the source line and the first source electrode are electrically connected to each other,
- wherein the bit line and the first drain electrode are electrically connected to each other,
- wherein the bit line is electrically connected to the first drain electrode through the third transistor,
- wherein the source line is electrically connected to the first source electrode through the fourth transistor,
- wherein the first transistor comprises a channel formation region provided in the substrate containing the semiconductor material, impurity regions provided so as to interpose the channel formation region, a first gate insulating layer over the channel formation region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode which are electrically connected to the impurity regions,
- wherein the signal line and the second gate electrode are electrically connected to each other;
- and
- wherein the word line, the other of the second source electrode and the second drain electrode, and the other electrode of the capacitor are electrically connected to one another.
19 more elements
Dependencies are inferred from the claim text.