Graphene-containing semiconductor structures and devices on a silicon carbide substrate having a defined miscut angle
AssigneeInternational Business Machines Corporation
InventorsChristos D. Dimitrakopoulos, Alfred Grill, Timothy J. McArdle, John A. Ott, Robert L. Wisnierff
Life of this patent
Estimating the term…
Abstract
A semiconductor structure having a high Hall mobility is provided that includes a SiC substrate having a miscut angle of 0.1° or less and a graphene layer located on an upper surface of the SiC substrate. Also, provided are semiconductor devices that include a SiC substrate having a miscut angle of 0.1° or less and at least one graphene-containing semiconductor device located atop the SiC substrate. The at least one graphene-containing semiconductor device includes a graphene layer overlying and in contact with an upper surface of the SiC substrate.
Claims16
A method of forming a semiconductor structure comprising:
- selecting a SiC substrate having a miscut angle of 0.1° or less;
- and
- forming a graphene layer on an upper surface of the SiC substrate, wherein said forming the graphene layer includes performing a first anneal in a dilute silane-containing ambient, and performing a second anneal at a temperature from 1400° C. to 1600° C. in an inert ambient.
A semiconductor device comprising:
- a SiC substrate having a miscut angle of 0.1° or less;
- and
- at least one graphene-containing semiconductor device located atop the SiC substrate, wherein said at least one graphene-containing semiconductor device includes a graphene layer overlying and in contact with an upper surface of the SiC substrate and a field effect transistor located on at least a portion of said graphene layer, said field effect transistor comprising a gate dielectric layer, a gate conductor, a source region and a drain region, wherein said gate dielectric layer has at least a first portion that extends beyond an outermost vertical sidewall of said source region, a second portion that extends beyond an outermost vertical sidewall of said drain region, and a third portion that is located between an innermost vertical sidewall of said source region and an innermost vertical sidewall of said drain region, wherein said gate conductor is in direct contact with said third portion of said gate dielectric layer.
Dependencies are inferred from the claim text.